Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936424AbcKWRaF (ORCPT ); Wed, 23 Nov 2016 12:30:05 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:36629 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757182AbcKWR3w (ORCPT ); Wed, 23 Nov 2016 12:29:52 -0500 From: Alexander Kochetkov To: daniel.lezcano@linaro.org, tglx@linutronix.de, heiko@sntech.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Alexander Kochetkov Subject: [PATCH 7/9] clocksource/drivers/rockchip_timer: implement clocksource timer Date: Wed, 23 Nov 2016 20:29:35 +0300 Message-Id: <1479922177-20136-7-git-send-email-al.kochet@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1479922177-20136-1-git-send-email-al.kochet@gmail.com> References: <1479922177-20136-1-git-send-email-al.kochet@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4482 Lines: 147 The patch implement stable clocksource for rk3188. It register one of the timers as clocksource and sched_clock. Also it override arm_global_timer clocksource using rating property (350). arm_global_timer enabled on rk3188 provide unstable clocksource. It's rate depend on ARM CPU rate. As result the command 'sleep 60' could run either ~60s (with CPU freq 312 MHZ) or ~45s (with CPU freq 1.6GHz). In order to use the patch you have to setup the timer using 'rockchip,clocksource' device tree property. timer6 was used as clocksource in kernel 3.0 from rockchip SDK. cpufreq-set -f 1.6GHZ date; sleep 60; date Signed-off-by: Alexander Kochetkov --- drivers/clocksource/rockchip_timer.c | 79 +++++++++++++++++++++++++++------- 1 file changed, 63 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index 61787c5..77bea97 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -42,7 +43,13 @@ struct rk_clock_event_device { struct rk_timer timer; }; +struct rk_clocksource { + struct clocksource cs; + struct rk_timer timer; +}; + static struct rk_clock_event_device bc_timer; +static struct rk_clocksource cs_timer; static inline struct rk_clock_event_device* rk_clock_event_device(struct clock_event_device *ce) @@ -139,14 +146,35 @@ static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } +static cycle_t rk_timer_clocksource_read(struct clocksource *cs) +{ + struct rk_clocksource *_cs = container_of(cs, struct rk_clocksource, cs); + return ~rk_timer_counter_read(&_cs->timer); +} + +static u64 notrace rk_timer_sched_clock_read(void) +{ + struct rk_clocksource *_cs = &cs_timer; + return ~rk_timer_counter_read(&_cs->timer); +} + static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg) { - struct clock_event_device *ce = &bc_timer.ce; - struct rk_timer *timer = &bc_timer.timer; + struct clock_event_device *ce = NULL; + struct clocksource *cs = NULL; + struct rk_timer *timer = NULL; struct clk *timer_clk; struct clk *pclk; int ret = -EINVAL, irq; + if (of_property_read_bool(np, "rockchip,clocksource")) { + cs = &cs_timer.cs; + timer = &cs_timer.timer; + } else { + ce = &bc_timer.ce; + timer = &bc_timer.timer; + } + timer->base = of_iomap(np, 0); if (!timer->base) { pr_err("Failed to get base address for '%s'\n", TIMER_NAME); @@ -189,26 +217,45 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg) goto out_irq; } - ce->name = TIMER_NAME; - ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_DYNIRQ; - ce->set_next_event = rk_timer_set_next_event; - ce->set_state_shutdown = rk_timer_shutdown; - ce->set_state_periodic = rk_timer_set_periodic; - ce->irq = irq; - ce->cpumask = cpu_possible_mask; - ce->rating = 250; + if (ce) { + ce->name = TIMER_NAME; + ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ; + ce->set_next_event = rk_timer_set_next_event; + ce->set_state_shutdown = rk_timer_shutdown; + ce->set_state_periodic = rk_timer_set_periodic; + ce->irq = irq; + ce->cpumask = cpu_possible_mask; + ce->rating = 250; + } + + if (cs) { + cs->name = TIMER_NAME; + cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; + cs->mask = CLOCKSOURCE_MASK(64); + cs->read = rk_timer_clocksource_read; + cs->rating = 350; + } rk_timer_interrupt_clear(timer); rk_timer_disable(timer); - ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce); - if (ret) { - pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret); - goto out_irq; + if (ce) { + ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce); + if (ret) { + pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret); + goto out_irq; + } + + clockevents_config_and_register(ce, timer->freq, 1, UINT_MAX); } - clockevents_config_and_register(ce, timer->freq, 1, UINT_MAX); + if (cs) { + rk_timer_update_counter(U64_MAX, timer); + rk_timer_enable(timer, 0); + clocksource_register_hz(cs, timer->freq); + sched_clock_register(rk_timer_sched_clock_read, 64, timer->freq); + } return 0; -- 1.7.9.5