Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750857AbcKWR35 (ORCPT ); Wed, 23 Nov 2016 12:29:57 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:35506 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754861AbcKWR3y (ORCPT ); Wed, 23 Nov 2016 12:29:54 -0500 From: Alexander Kochetkov To: daniel.lezcano@linaro.org, tglx@linutronix.de, heiko@sntech.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Alexander Kochetkov Subject: [PATCH 9/9] ARM: dts: rockchip: add timer entries to rk3188.dtsi Date: Wed, 23 Nov 2016 20:29:37 +0300 Message-Id: <1479922177-20136-9-git-send-email-al.kochet@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1479922177-20136-1-git-send-email-al.kochet@gmail.com> References: <1479922177-20136-1-git-send-email-al.kochet@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2135 Lines: 72 This is correct configuration borrowed from 3.0 kernel[1]. timer 6 used as clocksource, timers 0, 1, 4 and 5 used as clockevents. Timers can do interrupts and work as expected with correct driver support. [1] https://github.com/radxa/linux-rockchip/blob/radxa-stable-3.0/arch/arm/mach-rk3188/rk_timer.c Signed-off-by: Alexander Kochetkov --- arch/arm/boot/dts/rk3188.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 31f81b2..e2f88c8 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -106,6 +106,51 @@ }; }; + timer0: timer@20038000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x20038000 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + status = "disabled"; + }; + + timer1: timer@20038020 { + compatible = "rockchip,rk3288-timer"; + reg = <0x20038020 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + status = "disabled"; + }; + + timer4: timer@20038060 { + compatible = "rockchip,rk3288-timer"; + reg = <0x20038060 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER4>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + status = "disabled"; + }; + + timer5: timer@20038080 { + compatible = "rockchip,rk3288-timer"; + reg = <0x20038080 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER5>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + status = "disabled"; + }; + + timer6: timer@200380A0 { + compatible = "rockchip,rk3288-timer"; + reg = <0x200380A0 0x20>; + interrupts = ; + clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + status = "disabled"; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; -- 1.7.9.5