Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935318AbcKWXJW (ORCPT ); Wed, 23 Nov 2016 18:09:22 -0500 Received: from mail-ua0-f174.google.com ([209.85.217.174]:34302 "EHLO mail-ua0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934852AbcKWXJT (ORCPT ); Wed, 23 Nov 2016 18:09:19 -0500 MIME-Version: 1.0 In-Reply-To: <20161123004204.10851-1-stefan@agner.ch> References: <20161123004204.10851-1-stefan@agner.ch> From: Fabio Estevam Date: Wed, 23 Nov 2016 21:02:25 -0200 Message-ID: Subject: Re: [PATCH] ARM: dts: imx7d: fix LCDIF clock assignment To: Stefan Agner Cc: Shawn Guo , Sascha Hauer , Mark Rutland , "devicetree@vger.kernel.org" , linux-kernel , "robh+dt@kernel.org" , Peter Chen , Fabio Estevam , Liu Ying , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 925 Lines: 23 On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner wrote: > The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them > separately: > > Clock Clock Root Description > apb_clk MAIN_AXI_CLK_ROOT AXI clock > pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock > ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock > > All of them are switched by a single gate, which is part of the > IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for > the AXI bus clock (clock-name "axi") makes sure the gate gets > enabled when accessing registers. > > There seem to be no separate AXI display clock, and the clock is > optional. Hence remove the dummy clock. > > This fixes kernel freezes when starting the X-Server (which > disables/re-enables the display controller). > > Signed-off-by: Stefan Agner Reviewed-by: Fabio Estevam