Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756084AbcKXDEw (ORCPT ); Wed, 23 Nov 2016 22:04:52 -0500 Received: from mail-bn3nam01on0085.outbound.protection.outlook.com ([104.47.33.85]:59808 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754313AbcKXDEt (ORCPT ); Wed, 23 Nov 2016 22:04:49 -0500 X-Greylist: delayed 153394 seconds by postgrey-1.27 at vger.kernel.org; Wed, 23 Nov 2016 22:04:49 EST Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;nxp.com; dkim=none (message not signed) header.d=none; X-IncomingTopHeaderMarker: OriginalChecksum:;UpperCasedChecksum:;SizeAsReceived:706;Count:8 From: To: CC: , , , , , Tang Yuantian , Tang Yuantian Subject: [PATCH v3] clk: qoriq: added ls1012a clock configuration Date: Thu, 24 Nov 2016 10:36:55 +0800 Message-ID: <1479955015-37514-1-git-send-email-yuantian.tang@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-IncomingHeaderCount: 8 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131244294105229198;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() X-Forefront-Antispam-Report: CIP:192.88.168.50;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(1110001)(1109001)(336004)(339900001)(199003)(189002)(36756003)(5660300001)(97736004)(8936002)(8666005)(356003)(68736007)(305945005)(81166006)(2351001)(106466001)(81156014)(77096005)(105606002)(8676002)(50226002)(50986999)(92566002)(2906002)(5003940100001)(86362001)(104016004)(2876002)(33646002)(110136003)(38730400001)(50466002)(48376002)(189998001)(47776003)(7846002)(85426001)(6916009)(86152002)(626004)(6666003)(4326007)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:BN6PR03MB2467;H:tx30smr01.am.freescale.net;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:1;MX:1;LANG:en; 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+static const struct clockgen_muxinfo ls1012a_cmux = { + { + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, + {}, + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, + } +}; + static const struct clockgen_muxinfo t1023_hwa1 = { { {}, @@ -529,6 +537,16 @@ static const struct clockgen_chipinfo chipinfo[] = { .flags = CG_PLL_8BIT, }, { + .compat = "fsl,ls1012a-clockgen", + .cmux_groups = { + &ls1012a_cmux + }, + .cmux_to_group = { + 0, -1 + }, + .pll_mask = 0x03, + }, + { .compat = "fsl,ls2080a-clockgen", .cmux_groups = { &clockgen2_cmux_cga12, &clockgen2_cmux_cgb @@ -1316,6 +1334,7 @@ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); +CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); /* Legacy nodes */ -- 2.1.0.27.g96db324