Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S941062AbcKXMqH (ORCPT ); Thu, 24 Nov 2016 07:46:07 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42270 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936133AbcKXMqE (ORCPT ); Thu, 24 Nov 2016 07:46:04 -0500 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 24 Nov 2016 18:16:02 +0530 From: Abhishek Sahu To: Stephen Boyd Cc: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, mturquette@baylibre.com, galak@codeaurora.org, pradeepb@codeaurora.org, mmcclint@codeaurora.org, varada@codeaurora.org, sricharan@codeaurora.org, architt@codeaurora.org, ntelkar@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 4/7] clk: qcom: ipq4019: Added all the frequencies for apps cpu In-Reply-To: <20161102012450.GD16026@codeaurora.org> References: <1474460512-31994-1-git-send-email-absahu@codeaurora.org> <1474460512-31994-5-git-send-email-absahu@codeaurora.org> <20161102012450.GD16026@codeaurora.org> Message-ID: <356199897fb2022342a76bc872b703d5@codeaurora.org> User-Agent: Roundcube Webmail/1.2.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1895 Lines: 48 On 2016-11-02 06:54, Stephen Boyd wrote: > On 09/21, Abhishek Sahu wrote: >> The APPS CPU clock does not contain all the frequencies in its >> frequency table so this patch adds the same. >> >> Signed-off-by: Abhishek Sahu >> --- >> drivers/clk/qcom/gcc-ipq4019.c | 12 +++++++++++- >> 1 file changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/qcom/gcc-ipq4019.c >> b/drivers/clk/qcom/gcc-ipq4019.c >> index 211c68c..160e0cf 100644 >> --- a/drivers/clk/qcom/gcc-ipq4019.c >> +++ b/drivers/clk/qcom/gcc-ipq4019.c >> @@ -565,10 +565,20 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { >> }; >> >> static const struct freq_tbl ftbl_gcc_apps_clk[] = { >> - F(48000000, P_XO, 1, 0, 0), >> + F(48000000, P_XO, 1, 0, 0), >> F(200000000, P_FEPLL200, 1, 0, 0), >> + F(380000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(409000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(444000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(484000000, P_DDRPLLAPSS, 1, 0, 0), >> F(500000000, P_FEPLL500, 1, 0, 0), >> + F(507000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(532000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(560000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(592000000, P_DDRPLLAPSS, 1, 0, 0), >> F(626000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(666000000, P_DDRPLLAPSS, 1, 0, 0), >> + F(710000000, P_DDRPLLAPSS, 1, 0, 0), >> { } >> }; > > Can't we have the determine_rate callback know the speeds of the > "fixed" PLLs and use those first if the rate hits exactly? And > then if that doesn't happen go try ddrpllapps and set the rate on > it? I'm hoping we can get rid of this frequency table. This clock is being registered with QCOM clk_rcg2 operations which already has determine_rate callback based on this frequency table. Currently all the frequencies are being generated without HID divider but in future, we can have some frequency which will use dividers also. -- Abhishek Sahu