Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965844AbcKXOtU (ORCPT ); Thu, 24 Nov 2016 09:49:20 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:31675 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S941120AbcKXOrd (ORCPT ); Thu, 24 Nov 2016 09:47:33 -0500 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , CC: , , , , , , , , Subject: [PATCH v2 3/9] clk: stm32f4: Add post divisor for I2S & SAI PLLs Date: Thu, 24 Nov 2016 15:45:43 +0100 Message-ID: <1479998749-20358-4-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479998749-20358-1-git-send-email-gabriel.fernandez@st.com> References: <1479998749-20358-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-11-24_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2232 Lines: 79 From: Gabriel Fernandez This patch adds post dividers of I2S & SAI PLLs. These dividers are managed by a dedicated register (RCC_DCKCFGR). The PLL should be off before a set rate. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index c2b62cc..3918305 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -357,6 +357,18 @@ struct stm32f4_pll { #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) +struct stm32f4_pll_post_div_data { + u8 pll_num; + const char *name; + const char *parent; + u8 flag; + u8 offset; + u8 shift; + u8 width; + u8 flag_div; + const struct clk_div_table *div_table; +}; + struct stm32f4_vco_data { const char *vco_name; u8 offset; @@ -370,6 +382,18 @@ struct stm32f4_vco_data { { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 }, }; +#define MAX_POST_DIV 3 +static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { + { PLL_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, + + { PLL_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, + + { PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + STM32F4_RCC_DCKCFGR, 16, 2, CLK_DIVIDER_POWER_OF_TWO}, +}; + struct stm32f4_div_data { u8 shift; u8 width; @@ -996,6 +1020,23 @@ static void __init stm32f4_rcc_init(struct device_node *np) clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in", &data->pll_data[2], &stm32f4_clk_lock); + for (n = 0; n < MAX_POST_DIV; n++) { + const struct stm32f4_pll_post_div_data *post_div; + + post_div = &post_div_data[n]; + + clk_register_pll_div(post_div->name, + post_div->parent, + post_div->flag, + base + post_div->offset, + post_div->shift, + post_div->width, + post_div->flag_div, + post_div->div_table, + clks[post_div->pll_num], + &stm32f4_clk_lock); + } + sys_parents[1] = hse_clk; clk_register_mux_table( NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0, -- 1.9.1