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Subject: Re: Synopsys Ethernet QoS Driver
To: Joao Pinto <Joao.Pinto@synopsys.com>,
        Lars Persson <lars.persson@axis.com>
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CC: Rayagond Kokatanur <rayagond@vayavyalabs.com>,
        Rabin Vincent <rabin@rab.in>, mued dib <kreptor@gmail.com>,
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        <linux-arm-kernel@lists.infradead.org>
From: Giuseppe CAVALLARO <peppe.cavallaro@st.com>
Message-ID: <5d59aac4-1616-5316-a624-192b390d1569@st.com>
Date: Fri, 25 Nov 2016 09:55:39 +0100
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On 11/23/2016 12:43 PM, Joao Pinto wrote:
>> > Rabin Vincent can review and test that the port works properly on our Artpec-chips that use dwc_eth_qos.c today.
>> >
>> > The main porting step is to implement the device tree binding in bindings/net/snps,dwc-qos-ethernet.txt. Also our chip has a strict requirement that the phy is enabled when the SWR reset bit is set (it needs a tx clock to complete the reset).
>> >
>> > - Lars
> Ok, I will do the task.
>
> @Peppe: Agree with the plan?

Agree

peppe