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From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= <mans@mansr.com>
To: Mason <slash.tmp@free.fr>
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Subject: Re: Tearing down DMA transfer setup after DMA client has finished
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Date: Fri, 25 Nov 2016 14:12:49 +0000
In-Reply-To: <ae97a212-a91e-5e0a-c9b6-2dba3b79ddc5@free.fr> (Mason's message
        of "Fri, 25 Nov 2016 15:05:05 +0100")
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Mason <slash.tmp@free.fr> writes:

> On 25/11/2016 12:57, M?ns Rullg?rd wrote:
>
>> The same DMA unit is also used for SATA, which is an off the shelf
>> Designware controller with an in-kernel driver.  This interrupt timing
>> glitch can actually explain some intermittent errors I've observed with
>> it.
>
> FWIW, newer chips embed an AHCI controller, with a dedicated
> memory channel.
>
> FWIW2, the HW dev said memory channels are "almost free", and he
> would have no problem giving each device their own private channel
> read/write pair.

We still need to deal with the existing hardware.

-- 
M?ns Rullg?rd