From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= <mans@mansr.com>
To: Mason <slash.tmp@free.fr>
Cc: Russell King - ARM Linux <linux@armlinux.org.uk>,
        Vinod Koul <vinod.koul@intel.com>,
        Lars-Peter Clausen <lars@metafoo.de>,
        Dave Jiang <dave.jiang@intel.com>, Arnd Bergmann <arnd@arndb.de>,
        Mark Brown <broonie@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
        dmaengine@vger.kernel.org, Dan Williams <dan.j.williams@intel.com>,
        Jon Mason <jdmason@kudzu.us>, Lee Jones <lee.jones@linaro.org>,
        Maxime Ripard <maxime.ripard@free-electrons.com>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: Tearing down DMA transfer setup after DMA client has finished
References: <58356EA8.2010806@free.fr> <20161125045549.GC2698@localhost>
        <20161125124528.GJ14217@n2100.armlinux.org.uk>
        <yw1xtwav9092.fsf@unicorn.mansr.com>
        <20161125133436.GK14217@n2100.armlinux.org.uk>
        <yw1xlgw78y8k.fsf@unicorn.mansr.com>
        <20161125135830.GL14217@n2100.armlinux.org.uk>
        <yw1xh96v8xnb.fsf@unicorn.mansr.com>
        <20161125141708.GM14217@n2100.armlinux.org.uk>
        <d996bcdb-2413-770c-84d1-1b12ccd74477@free.fr>
        <yw1xoa137fvr.fsf@unicorn.mansr.com>
        <cba10848-57b1-c28c-2a60-83eb9da4cc63@free.fr>
Date: Fri, 25 Nov 2016 15:28:39 +0000
In-Reply-To: <cba10848-57b1-c28c-2a60-83eb9da4cc63@free.fr> (Mason's message
        of "Fri, 25 Nov 2016 16:21:49 +0100")
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Mason <slash.tmp@free.fr> writes:

> On 25/11/2016 16:12, M?ns Rullg?rd wrote:
>
>> Mason writes:
>> 
>>> I've had several talks with the HW dev, and I don't think they
>>> anticipated the need to mux the 3 channels. In their minds,
>>> customers would choose at most 3 devices to support, and
>>> assign one channel to each device statically.
>>>
>>> In fact, in tango4, supported devices are:
>>> A) NAND Flash controllers 0 and 1
>>> NB: the upstream driver only uses controller 0
>>> B) IDE or SATA controllers 0 and 1
>>> C) a few crypto HW blocks which do not work as expected (unused)
>>>
>>> Customers typically use 1 channel for NAND, maybe 1 for SATA,
>>> and 1 channel remains unused.
>> 
>> The hardware has two sata controllers, and I have a board that uses both.
>
> I don't have the tango3 client devices in mind, but
> 1 NAND + 2 SATA works out alright for 3 channels, right?

There are only two usable channels.

Besides, your 3.4 kernel allocates the channels dynamically, sort of,
but since it has a completely custom api, this particular timing issue
doesn't arise there.

-- 
M?ns Rullg?rd