Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932577AbcKYSyT (ORCPT ); Fri, 25 Nov 2016 13:54:19 -0500 Received: from mail-by2nam01on0048.outbound.protection.outlook.com ([104.47.34.48]:60960 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753474AbcKYSyJ (ORCPT ); Fri, 25 Nov 2016 13:54:09 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Serguei.Sagalovitch@amd.com; Subject: Re: Enabling peer to peer device transactions for PCIe devices To: =?UTF-8?Q?Christian_K=c3=b6nig?= , "Jason Gunthorpe" , Logan Gunthorpe References: <75a1f44f-c495-7d1e-7e1c-17e89555edba@amd.com> <45c6e878-bece-7987-aee7-0e940044158c@deltatee.com> <20161123190515.GA12146@obsidianresearch.com> <7bc38037-b6ab-943f-59db-6280e16901ab@amd.com> <20161123193228.GC12146@obsidianresearch.com> <20161123203332.GA15062@obsidianresearch.com> <20161123215510.GA16311@obsidianresearch.com> <91d28749-bc64-622f-56a1-26c00e6b462a@deltatee.com> <20161124164249.GD20818@obsidianresearch.com> <3f2d2db3-fb75-2422-2a18-a8497fd5d70e@amd.com> CC: Dan Williams , "Deucher, Alexander" , "linux-nvdimm@lists.01.org" , "linux-rdma@vger.kernel.org" , "linux-pci@vger.kernel.org" , "Kuehling, Felix" , "Bridgman, John" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "Sander, Ben" , "Suthikulpanit, Suravee" , "Blinzer, Paul" , "Linux-media@vger.kernel.org" , Haggai Eran From: Serguei Sagalovitch Message-ID: <7ff3cf70-b0c3-028e-fea8-c370a1185b65@amd.com> Date: Fri, 25 Nov 2016 12:16:30 -0500 User-Agent: Mozilla/5.0 (X11; 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Ie if I have a >> CPU mapped page and the GPU moves it to VRAM, it becomes non-cachable >> - do you still allow the CPU to access it? Or do you swap it back to >> cachable memory if the CPU touches it? > > Depends on the policy in command, but currently it's the other way > around most of the time. > > E.g. we allocate memory in VRAM, the CPU writes to it WC and avoids > reading because that is slow, the GPU in turn can access it with full > speed. > > When we run out of VRAM we move those allocations to system memory and > update both the CPU as well as the GPU page tables. > > So that move is transparent for both userspace as well as shaders > running on the GPU. I would like to add more in relation to CPU access : a) we could have CPU-accessible part of VRAM ("inside" of PCIe BAR register) and non-CPU accessible part. As the result if user needs to have CPU access than memory should be located in CPU-accessible part of VRAM or in system memory. Application/user mode driver could specify preference/hints of locations based on their assumption / knowledge about access patterns requirements, game resolution, knowledge about size of VRAM memory, etc. So if CPU access performance is critical then such memory should be allocated in system memory as the first (and may be only) choice. b) Allocation may not have CPU address at all - only GPU one. Also we may not be able to have CPU address/accesses for all VRAM memory but memory may still be migrated in any case unrelated if we have CPU address or not. c) " VRAM, it becomes non-cachable " Strictly speaking VRAM is configured as WC (write-combined memory) to provide fast CPU write access. Also it was found that sometimes if CPU access is not critical from performance perspective it may be useful to allocate/program system memory also as WC to avoid needs for extra "snooping" to synchronize with CPU caches during GPU access. So potentially system memory could be WC too.