Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755778AbcKYTuO (ORCPT ); Fri, 25 Nov 2016 14:50:14 -0500 Received: from mail-bn3nam01on0062.outbound.protection.outlook.com ([104.47.33.62]:17728 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754853AbcKYTuC (ORCPT ); Fri, 25 Nov 2016 14:50:02 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Serguei.Sagalovitch@amd.com; Subject: Re: Enabling peer to peer device transactions for PCIe devices To: Jason Gunthorpe References: <7bc38037-b6ab-943f-59db-6280e16901ab@amd.com> <20161123193228.GC12146@obsidianresearch.com> <20161123203332.GA15062@obsidianresearch.com> <20161123215510.GA16311@obsidianresearch.com> <91d28749-bc64-622f-56a1-26c00e6b462a@deltatee.com> <20161124164249.GD20818@obsidianresearch.com> <3f2d2db3-fb75-2422-2a18-a8497fd5d70e@amd.com> <7ff3cf70-b0c3-028e-fea8-c370a1185b65@amd.com> <20161125193410.GD16504@obsidianresearch.com> CC: =?UTF-8?Q?Christian_K=c3=b6nig?= , Logan Gunthorpe , Dan Williams , "Deucher, Alexander" , "linux-nvdimm@lists.01.org" , "linux-rdma@vger.kernel.org" , "linux-pci@vger.kernel.org" , "Kuehling, Felix" , "Bridgman, John" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "Sander, Ben" , "Suthikulpanit, Suravee" , "Blinzer, Paul" , "Linux-media@vger.kernel.org" , Haggai Eran From: Serguei Sagalovitch Message-ID: <80aae3e6-278e-49af-7d09-bea87ffd19e8@amd.com> Date: Fri, 25 Nov 2016 14:49:50 -0500 User-Agent: Mozilla/5.0 (X11; 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It is only issue for p2p without special interconnect and CPU access. Strictly speaking as long as we have "bus address" we could have RDMA but I agreed that for RDMA we could/should(?) always "request" CPU address (I hope that we could forget about 32-bit application :-)). BTW/FYI: About CPU access: Some user-level API is mainly handle based so there is no need for CPU access by default. About "visible" / non-visible VRAM parts: I assume that going forward we will be able to get rid from it completely as soon as support for resizable PCI BAR will be implemented and/or old/current h/w will become obsolete.