Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753628AbcK0JG1 (ORCPT ); Sun, 27 Nov 2016 04:06:27 -0500 Received: from mail-dm3nam03on0081.outbound.protection.outlook.com ([104.47.41.81]:63381 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753237AbcK0JGM (ORCPT ); Sun, 27 Nov 2016 04:06:12 -0500 X-Greylist: delayed 1027 seconds by postgrey-1.27 at vger.kernel.org; Sun, 27 Nov 2016 04:06:12 EST Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; X-IncomingTopHeaderMarker: OriginalChecksum:;UpperCasedChecksum:;SizeAsReceived:1655;Count:16 From: Naga Sureshkumar Relli To: , , , , CC: , , , Subject: [LINUX RFC v4 4/4] spi: zynqmp: gqspi: add support for stripe feature Date: Sun, 27 Nov 2016 14:03:42 +0530 Message-ID: <1480235622-34100-1-git-send-email-nagasure@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22724.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-IncomingHeaderCount: 16 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(189002)(199003)(90966002)(189998001)(4326007)(626004)(5003940100001)(52956003)(39400400001)(39450400002)(92566002)(2906002)(50986999)(39380400001)(39410400001)(36386004)(33646002)(46386002)(47776003)(45336002)(5001770100001)(48376002)(50226002)(103686003)(63266004)(5660300001)(356003)(36756003)(38730400001)(8936002)(6636002)(7846002)(106466001)(8676002)(2201001)(6862003)(42186005)(81166006)(81156014)(305945005)(50466002)(107986001)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR02MB1111;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; 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Signed-off-by: Naga Sureshkumar Relli --- Changes for v4: - No changes Changes for v3: - No change Changes for v2: - No change --- drivers/spi/spi-zynqmp-gqspi.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 18aeace..dc7cf03 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; * @dma_rx_bytes: Remaining bytes to receive by DMA mode * @dma_addr: DMA address after mapping the kernel buffer * @genfifoentry: Used for storing the genfifoentry instruction. + * @isinstr: To determine whether the transfer is instruction * @mode: Defines the mode in which QSPI is operating */ struct zynqmp_qspi { @@ -170,6 +171,7 @@ struct zynqmp_qspi { u32 dma_rx_bytes; dma_addr_t dma_addr; u32 genfifoentry; + bool isinstr; enum mode_type mode; }; @@ -404,11 +406,24 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) u32 genfifoentry = 0x0, statusreg; genfifoentry |= GQSPI_GENFIFO_MODE_SPI; + + + if (qspi->master->flags & SPI_MASTER_BOTH_CS) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + } else { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + genfifoentry |= xqspi->genfifobus; if (!is_high) { genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; + xqspi->isinstr = true; } else { genfifoentry |= GQSPI_GENFIFO_CS_HOLD; } @@ -665,6 +680,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + xqspi->isinstr = false; spi_finalize_current_transfer(master); ret = IRQ_HANDLED; } @@ -828,6 +844,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; + if ((!xqspi->isinstr) && (master->flags & SPI_MASTER_DATA_STRIPE)) + genfifoentry |= GQSPI_GENFIFO_STRIPE; + zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); if (xqspi->mode == GQSPI_MODE_DMA) @@ -980,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct resource *res; struct device *dev = &pdev->dev; + u32 num_cs; master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) @@ -1040,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (ret < 0) + master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + master->num_chipselect = num_cs; master->setup = zynqmp_qspi_setup; master->set_cs = zynqmp_qspi_chipselect; -- 2.10.2