Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753755AbcK0KIz (ORCPT ); Sun, 27 Nov 2016 05:08:55 -0500 Received: from mail-bl2nam02on0049.outbound.protection.outlook.com ([104.47.38.49]:64598 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753564AbcK0KIq (ORCPT ); Sun, 27 Nov 2016 05:08:46 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; X-IncomingTopHeaderMarker: OriginalChecksum:;UpperCasedChecksum:;SizeAsReceived:1660;Count:16 From: Naga Sureshkumar Relli To: , , , , CC: , , , Subject: [LINUX RFC v4 1/4] spi: adding support for data stripe feature in core Date: Sun, 27 Nov 2016 14:03:23 +0530 Message-ID: <1480235603-33890-1-git-send-email-nagasure@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22724.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-IncomingHeaderCount: 16 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(189002)(199003)(50986999)(106466001)(2906002)(4326007)(103686003)(92566002)(63266004)(42186005)(8936002)(81166006)(81156014)(5660300001)(33646002)(626004)(6862003)(50466002)(36756003)(48376002)(50226002)(6636002)(47776003)(38730400001)(36386004)(189998001)(45336002)(8676002)(5001770100001)(46386002)(305945005)(356003)(52956003)(39400400001)(7846002)(2201001)(39410400001)(5003940100001)(39380400001)(39450400002)(90966002)(107986001)(217873001)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN1PR02MB071;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;MX:1;A:1;LANG:en; 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This feature is required to support dual parallel mode of ZynqMP GQSPI controller. To achieve the same an API SPI_MASTER_DATA_STRIPE is added. With data stripe enabled, - even bytes i.e. 0, 2, 4,... are transmitted on lower data bus - odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus. To support data stripe; need to assert both chip selects once. This is achieved through API SPI_MASTER_BOTH_CS. Signed-off-by: Naga Sureshkumar Relli --- Changes for v4: - No changes, sending the previous one as is Change for v3: - Updated comments for newly added APIs - Changed patch description for ease of understanding Changes for v2: - Added error handling condition for newly added features --- drivers/spi/spi.c | 8 ++++++++ include/linux/spi/spi.h | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 5787b72..01980af 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2538,6 +2538,14 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) if (list_empty(&message->transfers)) return -EINVAL; + /* + * Data stripe option is selected if and only if when + * two chips are enabled + */ + if ((master->flags & SPI_MASTER_DATA_STRIPE) + && !(master->flags & SPI_MASTER_BOTH_CS)) + return -EINVAL; + /* Half-duplex links include original MicroWire, and ones with * only one data pin like SPI_3WIRE (switches direction) or where * either MOSI or MISO is missing. They can also be caused by diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 4b743ac..94a5e6a 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -443,6 +443,17 @@ struct spi_master { #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ + /* Controller may support data stripe feature when more than one + * chips are present. + * Setting data stripe will send data in following manner: + * -> even bytes i.e. 0, 2, 4,... are transmitted on lower data bus + * -> odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus + */ +#define SPI_MASTER_DATA_STRIPE BIT(7) /* support data stripe */ + /* Controller may support asserting more than one chip select at once. + * This flag will enable that feature. + */ +#define SPI_MASTER_BOTH_CS BIT(8) /* assert both chip selects */ /* * on some hardware transfer / message size may be constrained * the limit may depend on device transfer settings -- 2.10.2