Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753990AbcK1FZJ (ORCPT ); Mon, 28 Nov 2016 00:25:09 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:57594 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752038AbcK1FZE (ORCPT ); Mon, 28 Nov 2016 00:25:04 -0500 Subject: Re: [PATCH] ARM: dts: da850: specify the maximum bandwidth for tilcdc To: Bartosz Golaszewski , Kevin Hilman , Michael Turquette , Rob Herring , Frank Rowand , Mark Rutland , Peter Ujfalusi , Russell King References: <1480088245-8368-1-git-send-email-bgolaszewski@baylibre.com> CC: LKML , arm-soc , linux-drm , linux-devicetree , Jyri Sarha , Tomi Valkeinen , David Airlie , Laurent Pinchart From: Sekhar Nori Message-ID: <8829c208-0674-43c0-8449-ef764071583f@ti.com> Date: Mon, 28 Nov 2016 10:54:01 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1480088245-8368-1-git-send-email-bgolaszewski@baylibre.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 984 Lines: 28 On Friday 25 November 2016 09:07 PM, Bartosz Golaszewski wrote: > It has been determined that the maximum resolution supported correctly > by tilcdc rev1 on da850 SoCs is 800x600@60. Due to memory throughput > constraints we must filter out higher modes. > > Specify the max-bandwidth property for the display node for > da850-based boards. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm/boot/dts/da850.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi > index 8e30d9b..9b7c444 100644 > --- a/arch/arm/boot/dts/da850.dtsi > +++ b/arch/arm/boot/dts/da850.dtsi > @@ -452,6 +452,7 @@ > compatible = "ti,da850-tilcdc"; > reg = <0x213000 0x1000>; > interrupts = <52>; > + max-bandwidth = <28800000>; If this is effectively the max pixel clock that the device supports, then why not use the datasheet specified value of 37.5 MHz (Tc = 26.66 ns). Thanks, Sekhar