Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756203AbcK2G5n (ORCPT ); Tue, 29 Nov 2016 01:57:43 -0500 Received: from mail-pg0-f44.google.com ([74.125.83.44]:35553 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755908AbcK2G5a (ORCPT ); Tue, 29 Nov 2016 01:57:30 -0500 Date: Tue, 29 Nov 2016 12:27:26 +0530 From: Viresh Kumar To: Stephen Boyd Cc: Kevin Hilman , Vincent Guittot , Rob Herring , Rafael Wysocki , "linaro-kernel@lists.linaro.org" , "linux-pm@vger.kernel.org" , linux-kernel , Mark Rutland , Ulf Hansson , Lina Iyer , "devicetree@vger.kernel.org" , Nayak Rajendra Subject: Re: [PATCH 1/2] PM / Domains: Introduce domain-performance-state binding Message-ID: <20161129065726.GG3288@vireshk-i7> References: <20161121150708.j4gosfr2uetc7mwp@rob-hp-laptop> <20161122031717.GE10014@vireshk-i7> <20161124020322.GI6095@codeaurora.org> <20161124044020.GC9376@vireshk-i7> <4f815e31-22d0-fef7-953c-257fa2bbcb9d@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4f815e31-22d0-fef7-953c-257fa2bbcb9d@codeaurora.org> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1435 Lines: 63 On 28-11-16, 10:27, Stephen Boyd wrote: > On 11/23/2016 08:40 PM, Viresh Kumar wrote: > > But even in these cases we wouldn't be using the voltage values within the > > kernel as we will be giving only a performance state to the M3 core, right? > > Nope. In these cases we need to set a certain voltage and we do that by > requesting it via the M3 core. Don't we need something like this then ? parent: power-controller@12340000 { compatible = "foo,power-controller"; reg = <0x12340000 0x1000>; #power-domain-cells = <0>; domain-performance-states = <&perf_state0>; }; perf_state0: performance_states { pstate1: pstate@1 { index = <1>; /* Optional */ microvolt = <970000 975000 985000>; }; pstate2: pstate@2 { index = <2>; /* Optional */ microvolt = <970000 975000 985000>; }; pstate3: pstate@3 { index = <3>; /* Optional */ microvolt = <970000 975000 985000>; }; } cpus { cpu@0 { ... power-domain = <&parent>; operating-points-v2 = <&cpu0_opp_table>; }; }; cpu0_opp_table: opp_table0 { compatible = "operating-points-v2"; opp-shared; opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; domain-performance-state = <&pstate1>; }; opp@1100000000 { opp-hz = /bits/ 64 <1100000000>; domain-performance-state = <&pstate2>; }; opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; domain-performance-state = <&pstate3>; }; }; -- viresh