Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933519AbcK2L5u (ORCPT ); Tue, 29 Nov 2016 06:57:50 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:36119 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756987AbcK2L5L (ORCPT ); Tue, 29 Nov 2016 06:57:11 -0500 From: Bartosz Golaszewski To: Kevin Hilman , Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Peter Ujfalusi , Russell King Cc: LKML , arm-soc , linux-drm , linux-devicetree , Jyri Sarha , Tomi Valkeinen , David Airlie , Laurent Pinchart , Bartosz Golaszewski Subject: [PATCH v3 2/2] ARM: dts: da850: specify the maximum pixel clock rate for tilcdc Date: Tue, 29 Nov 2016 12:57:04 +0100 Message-Id: <1480420624-23544-3-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1480420624-23544-1-git-send-email-bgolaszewski@baylibre.com> References: <1480420624-23544-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 878 Lines: 28 At maximum CPU frequency of 300 MHz the maximum pixel clock frequency is 37.5 MHz[1]. We must filter out any mode for which the calculated pixel clock rate would exceed this value. Specify the max-pixelclock property for the display node for da850-lcdk. [1] http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_(LCDC)_Throughput_and_Optimization_Techniques Signed-off-by: Bartosz Golaszewski --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 5f4ba2e..00692d3 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -453,6 +453,7 @@ compatible = "ti,da850-tilcdc"; reg = <0x213000 0x1000>; interrupts = <52>; + max-pixelclock = <37500>; status = "disabled"; ports { -- 2.9.3