Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756225AbcK2RbM (ORCPT ); Tue, 29 Nov 2016 12:31:12 -0500 Received: from merlin.infradead.org ([205.233.59.134]:40514 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755029AbcK2RbD (ORCPT ); Tue, 29 Nov 2016 12:31:03 -0500 Date: Tue, 29 Nov 2016 18:30:55 +0100 From: Peter Zijlstra To: Stephane Eranian Cc: "Liang, Kan" , "mingo@redhat.com" , LKML , Alexander Shishkin , "ak@linux.intel.com" , "Odzioba, Lukasz" Subject: Re: [PATCH] perf/x86: fix event counter update issue Message-ID: <20161129173055.GP3092@twins.programming.kicks-ass.net> References: <1480361206-1702-1-git-send-email-kan.liang@intel.com> <20161129092520.GB3092@twins.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23.1 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 865 Lines: 22 On Tue, Nov 29, 2016 at 09:20:10AM -0800, Stephane Eranian wrote: > Max period is limited by the number of bits the kernel can write to an MSR. > Used to be 31, now it is 47 for core PMU as per patch pointed to by Kan. No, I think it sets it to 48 now, which is the problem. It should be 1 bit less than the total width. So something like so. diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a74a2dbc0180..cb8522290e6a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) /* Support full width counters using alternative MSR range */ if (x86_pmu.intel_cap.full_width_write) { - x86_pmu.max_period = x86_pmu.cntval_mask; + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; x86_pmu.perfctr = MSR_IA32_PMC0; pr_cont("full-width counters, "); }