From: "Liang, Kan" <kan.liang@intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
        Stephane Eranian <eranian@google.com>
CC: "mingo@redhat.com" <mingo@redhat.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        "ak@linux.intel.com" <ak@linux.intel.com>,
        "Odzioba, Lukasz" <lukasz.odzioba@intel.com>
Subject: RE: [PATCH] perf/x86: fix event counter update issue
Thread-Topic: [PATCH] perf/x86: fix event counter update issue
Thread-Index: AQHSSa1zo+RK785pc06zvVqph8o/bKDvK4oAgACEqwCAAAMBgIAAnoVQ
Date: Tue, 29 Nov 2016 19:07:25 +0000
Message-ID: <37D7C6CF3E00A74B8858931C1DB2F07750CA4225@SHSMSX103.ccr.corp.intel.com>
References: <1480361206-1702-1-git-send-email-kan.liang@intel.com>
 <20161129092520.GB3092@twins.programming.kicks-ass.net>
 <CABPqkBQPRBZZB8wbhYGLoS9ww_0vQrt=nkqgDC_fFgG99cqdCg@mail.gmail.com>
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> On Tue, Nov 29, 2016 at 09:20:10AM -0800, Stephane Eranian wrote:
> > Max period is limited by the number of bits the kernel can write to an
> MSR.
> > Used to be 31, now it is 47 for core PMU as per patch pointed to by Kan.
> 
> No, I think it sets it to 48 now, which is the problem. It should be 1 bit less
> than the total width.
> 
> So something like so.
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index a74a2dbc0180..cb8522290e6a 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void)
> 
>  	/* Support full width counters using alternative MSR range */
>  	if (x86_pmu.intel_cap.full_width_write) {
> -		x86_pmu.max_period = x86_pmu.cntval_mask;
> +		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
>  		x86_pmu.perfctr = MSR_IA32_PMC0;
>  		pr_cont("full-width counters, ");
>  	}

It doesn't work. 
perf stat -x, -C1 -e cycles -- sudo taskset 0x2 ./loop 100000000000
18446743727217821696,,cycles,313837854019,100.00

delta 0xffffff8000001803 new 0x1804 prev 0xffffff8000000001

I guess we need at least x86_pmu.cntval_mask >> 2 to prevent
the sign flag set.
I'm testing it now.


Also, no matter how it's fixed. I think we'd better add WARN_ONCE
for delta.

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 6c3b0ef..2ce8299 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -100,6 +100,9 @@ u64 x86_perf_event_update(struct perf_event *event)
 	delta = (new_raw_count << shift) - (prev_raw_count << shift);
 	delta >>= shift;
 
+	WARN_ONCE((delta < 0), "counter increment must be positive. delta 0x%llx new 0x%llx prev 0x%llx\n",
+		  delta, new_raw_count, prev_raw_count);
+
 	local64_add(delta, &event->count);
 	local64_sub(delta, &hwc->period_left);

Thanks,
Kan