Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756951AbcK2Udk convert rfc822-to-8bit (ORCPT ); Tue, 29 Nov 2016 15:33:40 -0500 Received: from mga06.intel.com ([134.134.136.31]:59701 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751991AbcK2Udc (ORCPT ); Tue, 29 Nov 2016 15:33:32 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,570,1473145200"; d="scan'208";a="35601487" From: "Liang, Kan" To: Peter Zijlstra CC: Stephane Eranian , "mingo@redhat.com" , LKML , Alexander Shishkin , "ak@linux.intel.com" , "Odzioba, Lukasz" Subject: RE: [PATCH] perf/x86: fix event counter update issue Thread-Topic: [PATCH] perf/x86: fix event counter update issue Thread-Index: AQHSSa1zo+RK785pc06zvVqph8o/bKDvK4oAgACEqwCAAAMBgIAAnoVQ//+DUYCAAJTSIA== Date: Tue, 29 Nov 2016 20:33:28 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F07750CA42A3@SHSMSX103.ccr.corp.intel.com> References: <1480361206-1702-1-git-send-email-kan.liang@intel.com> <20161129092520.GB3092@twins.programming.kicks-ass.net> <20161129173055.GP3092@twins.programming.kicks-ass.net> <37D7C6CF3E00A74B8858931C1DB2F07750CA4225@SHSMSX103.ccr.corp.intel.com> <20161129193201.GE3045@worktop.programming.kicks-ass.net> In-Reply-To: <20161129193201.GE3045@worktop.programming.kicks-ass.net> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODAzMzk1NjItZDA0Yi00ODNmLWE2MTEtYzI2ZTA3YzgwMTI4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IloyM0FOcHd6RVwvQ1pscU85Um5FNm4zU0o4cDZEOTZmeWg4RFdhOWRvcU44PSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2010 Lines: 57 > On Tue, Nov 29, 2016 at 07:07:25PM +0000, Liang, Kan wrote: > > > diff --git a/arch/x86/events/intel/core.c > > > b/arch/x86/events/intel/core.c index a74a2dbc0180..cb8522290e6a > > > 100644 > > > --- a/arch/x86/events/intel/core.c > > > +++ b/arch/x86/events/intel/core.c > > > @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) > > > > > > /* Support full width counters using alternative MSR range */ > > > if (x86_pmu.intel_cap.full_width_write) { > > > - x86_pmu.max_period = x86_pmu.cntval_mask; > > > + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; > > > x86_pmu.perfctr = MSR_IA32_PMC0; > > > pr_cont("full-width counters, "); > > > } > > > > It doesn't work. > > perf stat -x, -C1 -e cycles -- sudo taskset 0x2 ./loop 100000000000 > > 18446743727217821696,,cycles,313837854019,100.00 > > > > delta 0xffffff8000001803 new 0x1804 prev 0xffffff8000000001 > > > > I guess we need at least x86_pmu.cntval_mask >> 2 to prevent the sign > > flag set. > > Possible delta should be u64, as we know the counter cannot decrement. Yes, the patch as below fixes the issue on my SLM. diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6c3b0ef..abd97e8 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -69,7 +69,7 @@ u64 x86_perf_event_update(struct perf_event *event) int shift = 64 - x86_pmu.cntval_bits; u64 prev_raw_count, new_raw_count; int idx = hwc->idx; - s64 delta; + u64 delta; if (idx == INTEL_PMC_IDX_FIXED_BTS) return 0; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a74a2db..cb85222 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) /* Support full width counters using alternative MSR range */ if (x86_pmu.intel_cap.full_width_write) { - x86_pmu.max_period = x86_pmu.cntval_mask; + x86_pmu.max_period = x86_pmu.cntval_mask >> 1; x86_pmu.perfctr = MSR_IA32_PMC0; pr_cont("full-width counters, "); }