Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933828AbcK3JvS (ORCPT ); Wed, 30 Nov 2016 04:51:18 -0500 Received: from mail-pg0-f46.google.com ([74.125.83.46]:36125 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933689AbcK3Ju4 (ORCPT ); Wed, 30 Nov 2016 04:50:56 -0500 From: Baoyou Xie To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, shawnguo@kernel.org, jun.nie@linaro.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn, chen.chaokai@zte.com.cn, wang.qiang01@zte.com.cn Subject: [PATCH v2] arm64: dts: zx: add zx296718's topcrm node Date: Wed, 30 Nov 2016 17:50:18 +0800 Message-Id: <1480499418-13905-1-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2643 Lines: 104 Enable topcrm clock node for zx296718, which is used for CPU's frequency change. Furthermore, this patch adds the CPU clock phandle in CPU's node and uses operating-points-v2 to register operating points. So it can be used by cpufreq-dt driver. Signed-off-by: Baoyou Xie --- arch/arm64/boot/dts/zte/zx296718.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 6b239a3..992158a 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include / { compatible = "zte,zx296718"; @@ -81,6 +82,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -88,6 +91,7 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -95,6 +99,7 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -102,6 +107,38 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <857000>; + clock-latency-ns = <500000>; + }; + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <857000>; + clock-latency-ns = <500000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <882000>; + clock-latency-ns = <500000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <892000>; + clock-latency-ns = <500000>; + }; + opp@1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1009000>; + clock-latency-ns = <500000>; }; }; @@ -279,6 +316,12 @@ dma-requests = <32>; }; + topcrm: clock-controller@1461000 { + compatible = "zte,zx296718-topcrm"; + reg = <0x01461000 0x1000>; + #clock-cells = <1>; + }; + sysctrl: sysctrl@1463000 { compatible = "zte,zx296718-sysctrl", "syscon"; reg = <0x1463000 0x1000>; -- 2.7.4