Date: Wed, 30 Nov 2016 12:01:45 -0600
From: atull <atull@opensource.altera.com>
To: Joshua Clayton <stillcompiling@gmail.com>
CC: Moritz Fischer <moritz.fischer@ettus.com>,
        Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
        Russell King <linux@armlinux.org.uk>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 0/3] Altera Cyclone Passive Serial SPI FPGA Manager
In-Reply-To: <cover.1480467185.git.stillcompiling@gmail.com>
Message-ID: <alpine.DEB.2.10.1611301150270.2617@atull-730U3E-740U3E>
References: <cover.1480467185.git.stillcompiling@gmail.com>
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On Wed, 30 Nov 2016, Joshua Clayton wrote:

Hi Joshua,

The DT bindings will need Rob Herring's ack.  The bitrev.h
changes will need Russell King's ack.

I've made some comments on patch 3/3 but it looks good to me
besides that.

Once we have those other acks, please submit your v4 including fixes
for my comments and whatever else comes up.  I'm hoping it will be
minor and with that done, v4 can go in.

When you send in v4, please also cc our new mailing list that Moritz
made: linux-fpga@vger.kernel.org

Alan

> This series adds an FPGA manager for Altera cyclone FPGAs
> that can program them using an spi port and a couple of gpios, using
> Alteras passive serial protocol.
> 
> Changes from v2:
> 
> - Merged patch 3 and 4 as suggested in review by Moritz Fischer
> - Changed FPGA_MIN_DELAY from 250 to 50 ms is the time advertized by
>   Altera. This now works, as we don't assume it is done
> 
> Changes from v1:
> - Changed the name from cyclone-spi-fpga-mgr to cyclone-ps-spi-fpga-mgr
>   This name change was requested by Alan Tull, to be specific about which
>   programming method is being employed on the fpga.
> - Changed the name of the reset-gpio to config-gpio to closer match the
>   way the pins are described in the Altera manual
> - Moved MODULE_LICENCE, _AUTHOR, and _DESCRIPTION to the bottom
> 
> - Added a bitrev8x4() function to the bitrev headers and implemented ARM
>  const, runtime, and ARM specific faster versions (This may end up
>  needing to be a standalone patch)
> 
> - Moved the bitswapping into cyclonespi_write(), as requested.
>   This falls short of my desired generic lsb first spi support, but is a step
>   in that direction.
> 
> - Fixed whitespace problems introduced during refactoring
> 
> - Replaced magic number for initial delay with a descriptive macro
> - Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
> 
> Joshua Clayton (3):
>   lib: add bitrev8x4()
>   doc: dt: add cyclone-spi binding document
>   fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
> 
>  .../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt      |  23 +++
>  arch/arm/include/asm/bitrev.h                      |   5 +
>  drivers/fpga/Kconfig                               |   7 +
>  drivers/fpga/Makefile                              |   1 +
>  drivers/fpga/cyclone-ps-spi.c                      | 176 +++++++++++++++++++++
>  include/linux/bitrev.h                             |  26 +++
>  6 files changed, 238 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga-mgr.txt
>  create mode 100644 drivers/fpga/cyclone-ps-spi.c
> 
> -- 
> 2.9.3
> 
>