Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758292AbcK3TMR (ORCPT ); Wed, 30 Nov 2016 14:12:17 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34024 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758160AbcK3TMK (ORCPT ); Wed, 30 Nov 2016 14:12:10 -0500 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 34AD1614E5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=sboyd@codeaurora.org Date: Wed, 30 Nov 2016 11:12:07 -0800 From: Stephen Boyd To: Vivek Gautam Cc: kishon , robh+dt , Mark Rutland , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Message-ID: <20161130191207.GJ6095@codeaurora.org> References: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> <1479816163-5260-4-git-send-email-vivek.gautam@codeaurora.org> <20161128225543.GM6095@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1977 Lines: 48 On 11/29, Vivek Gautam wrote: > On Tue, Nov 29, 2016 at 4:25 AM, Stephen Boyd wrote: > > On 11/22, Vivek Gautam wrote: > >> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > >> new file mode 100644 > >> index 0000000..ffb173b > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > >> @@ -0,0 +1,74 @@ > > > > >> + "pipe" for pipe clock specific to > >> + each port/lane (Optional). > > > > The pipe clocks are orphaned right now. We should add an output > > clock from the phy to go into the controller and back into the > > phy if I recall correctly. The phy should be a clock provider > > itself so it can output the pipe clock source into GCC and back > > into the phy and controller. > > > >> + - resets: a list of phandles and reset controller specifier pairs, > >> + one for each entry in reset-names. > >> + - reset-names: must be "phy" for reset of phy block, > >> + "common" for phy common block reset, > >> + "cfg" for phy's ahb cfg block reset (Optional). > >> + "port" for reset specific to > >> + each port/lane (Optional). > >> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block. > >> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. > >> + > >> +Optional properties: > >> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk > >> + pll block. > >> + > >> +Example: > >> + pcie_phy: pciephy@34000 { > > > > pcie-phy or just phy as the node name? > > How about just 'phy'? The label pcie_phy anyways explains the use. > > phy is a great color choice for the shed. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project