Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758766AbcK3Uqb convert rfc822-to-8bit (ORCPT ); Wed, 30 Nov 2016 15:46:31 -0500 Received: from mx5-phx2.redhat.com ([209.132.183.37]:47059 "EHLO mx5-phx2.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755971AbcK3Up6 (ORCPT ); Wed, 30 Nov 2016 15:45:58 -0500 Date: Wed, 30 Nov 2016 15:45:55 -0500 (EST) From: Paolo Bonzini To: David Matlack Cc: kvm list , linux-kernel@vger.kernel.org, Jim Mattson , Radim =?utf-8?B?S3LEjW3DocWZ?= Message-ID: <1271508271.857704.1480538755857.JavaMail.zimbra@redhat.com> In-Reply-To: References: <1480472050-58023-1-git-send-email-dmatlack@google.com> <1480472050-58023-2-git-send-email-dmatlack@google.com> <59bf4f3c-34ab-5cbc-9579-f1a8648804ea@redhat.com> Subject: Re: [PATCH v3 1/5] KVM: nVMX: generate non-true VMX MSRs based on true versions MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT X-Originating-IP: [10.4.164.1, 10.5.101.130] X-Mailer: Zimbra 8.0.6_GA_5922 (ZimbraWebClient - FF50 (Linux)/8.0.6_GA_5922) Thread-Topic: nVMX: generate non-true VMX MSRs based on true versions Thread-Index: SL/AxbfPws2GHFl6xpVO9qIyuLgEfA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1496 Lines: 35 ----- Original Message ----- > From: "David Matlack" > To: "Paolo Bonzini" > Cc: "kvm list" , linux-kernel@vger.kernel.org, "Jim Mattson" , "Radim > Krčmář" > Sent: Wednesday, November 30, 2016 7:05:04 PM > Subject: Re: [PATCH v3 1/5] KVM: nVMX: generate non-true VMX MSRs based on true versions > > On Wed, Nov 30, 2016 at 3:16 AM, Paolo Bonzini wrote: > > On 30/11/2016 03:14, David Matlack wrote: > >> > >> /* secondary cpu-based controls */ > >> @@ -2868,36 +2865,32 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, > >> u32 msr_index, u64 *pdata) > >> *pdata = vmx_control_msr( > >> vmx->nested.nested_vmx_pinbased_ctls_low, > >> vmx->nested.nested_vmx_pinbased_ctls_high); > >> + if (msr_index == MSR_IA32_VMX_PINBASED_CTLS) > >> + *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; > > > > Almost: PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR must be > > added to both the low and high parts. Likewise below. > > I guess you can use vmx_control_msr to generate it, too. > > SGTM. > > Although that would mean the true MSRs indicate a bit must-be-0 while > the non-true MSRs are indicating it must-be-1, which seems odd. You're right. the high part is "can be 1", so the true MSR's high part must already include the always-on-without-true-MSR bits. Good! Paolo