Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760044AbcLAP3q (ORCPT ); Thu, 1 Dec 2016 10:29:46 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:54324 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1759857AbcLAP25 (ORCPT ); Thu, 1 Dec 2016 10:28:57 -0500 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , CC: , , , , , , , , Subject: [PATCH v3 5/9] clk: stm32f4: Add I2S clock Date: Thu, 1 Dec 2016 16:27:45 +0100 Message-ID: <1480606069-5178-6-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> References: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-12-01_12:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1719 Lines: 58 From: Gabriel Fernandez This patch introduces I2S clock for stm32f4 soc. The I2S clock could be derived from an external clock or from pll-i2s Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 86244fc..3063b30 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -935,6 +935,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, static const char *lcd_parent[1] = { "pllsai-r-div" }; +static const char *i2s_parents[2] = { "plli2s-r", NULL }; + struct stm32_aux_clk { int idx; const char *name; @@ -969,6 +971,12 @@ struct stm32f4_clk_data { STM32F4_RCC_APB2ENR, 26, CLK_SET_RATE_PARENT }, + { + CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents), + STM32F4_RCC_CFGR, 23, 1, + NO_GATE, 0, + CLK_SET_RATE_PARENT + }, }; static const struct stm32f4_clk_data stm32f429_clk_data = { @@ -1063,7 +1071,7 @@ static struct clk_hw *stm32_register_aux_clk(const char *name, static void __init stm32f4_rcc_init(struct device_node *np) { - const char *hse_clk; + const char *hse_clk, *i2s_in_clk; int n; const struct of_device_id *match; const struct stm32f4_clk_data *data; @@ -1098,6 +1106,10 @@ static void __init stm32f4_rcc_init(struct device_node *np) hse_clk = of_clk_get_parent_name(np, 0); + i2s_in_clk = of_clk_get_parent_name(np, 1); + + i2s_parents[1] = i2s_in_clk; + clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, 16000000, 160000); pllcfgr = readl(base + STM32F4_RCC_PLLCFGR); -- 1.9.1