Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759644AbcLAP2w (ORCPT ); Thu, 1 Dec 2016 10:28:52 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:17779 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753741AbcLAP2t (ORCPT ); Thu, 1 Dec 2016 10:28:49 -0500 From: To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , , , CC: , , , , , , , , Subject: [PATCH v3 6/9] clk: stm32f4: Add SAI clocks Date: Thu, 1 Dec 2016 16:27:46 +0100 Message-ID: <1480606069-5178-7-git-send-email-gabriel.fernandez@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> References: <1480606069-5178-1-git-send-email-gabriel.fernandez@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.1.80] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-12-01_12:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1476 Lines: 52 From: Gabriel Fernandez This patch introduces SAI clocks for stm32f4 socs. Signed-off-by: Gabriel Fernandez --- drivers/clk/clk-stm32f4.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 3063b30..02339d1 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -937,6 +937,9 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, static const char *i2s_parents[2] = { "plli2s-r", NULL }; +static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL, + "no-clock" }; + struct stm32_aux_clk { int idx; const char *name; @@ -977,6 +980,18 @@ struct stm32f4_clk_data { NO_GATE, 0, CLK_SET_RATE_PARENT }, + { + CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents), + STM32F4_RCC_DCKCFGR, 20, 3, + STM32F4_RCC_APB2ENR, 22, + CLK_SET_RATE_PARENT + }, + { + CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents), + STM32F4_RCC_DCKCFGR, 22, 3, + STM32F4_RCC_APB2ENR, 22, + CLK_SET_RATE_PARENT + }, }; static const struct stm32f4_clk_data stm32f429_clk_data = { @@ -1109,6 +1124,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) i2s_in_clk = of_clk_get_parent_name(np, 1); i2s_parents[1] = i2s_in_clk; + sai_parents[2] = i2s_in_clk; clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0, 16000000, 160000); -- 1.9.1