Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760289AbcLBRHq (ORCPT ); Fri, 2 Dec 2016 12:07:46 -0500 Received: from mail-ua0-f181.google.com ([209.85.217.181]:32878 "EHLO mail-ua0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760049AbcLBRHo (ORCPT ); Fri, 2 Dec 2016 12:07:44 -0500 MIME-Version: 1.0 In-Reply-To: References: <0a21157c2233ba7d0781bbf07866b3f2d7e7c25d.1480638597.git.luto@kernel.org> From: Andy Lutomirski Date: Fri, 2 Dec 2016 09:07:12 -0800 Message-ID: Subject: Re: [PATCH v2 5/6] x86/xen: Add a Xen-specific sync_core() implementation To: Andrew Cooper , Linus Torvalds Cc: Boris Ostrovsky , Xen-devel List , Juergen Gross , Borislav Petkov , Matthew Whitehead , One Thousand Gnomes , Henrique de Moraes Holschuh , Brian Gerst , "linux-kernel@vger.kernel.org" , X86 ML , Peter Zijlstra Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2044 Lines: 50 On Dec 2, 2016 3:44 AM, "Andrew Cooper" wrote: > > On 02/12/16 00:35, Andy Lutomirski wrote: > > On Xen PV, CPUID is likely to trap, and Xen hypercalls aren't > > guaranteed to serialize. (Even CPUID isn't *really* guaranteed to > > serialize on Xen PV, but, in practice, any trap it generates will > > serialize.) > > Well, Xen will enabled CPUID Faulting wherever it can, which is > realistically all IvyBridge hardware and newer. > > All hypercalls are a privilege change to cpl0. I'd hope this condition > is serialising, but I can't actually find any documentation proving or > disproving this. I don't know for sure. IRET is serializing, and if Xen returns using IRET, we're fine. > > > > > On my laptop, CPUID(eax=1, ecx=0) is ~83ns and IRET-to-self is > > ~110ns. But Xen PV will trap CPUID if possible, so IRET-to-self > > should end up being a nice speedup. > > > > Cc: Andrew Cooper > > Signed-off-by: Andy Lutomirski > > CC'ing xen-devel and the Xen maintainers in Linux. > > As this is the only email from this series in my inbox, I will say this > here, but it should really be against patch 6. > > A write to %cr2 is apparently (http://sandpile.org/x86/coherent.htm) not > serialising on the 486, but I don't have a manual to hand to check. I'll quote the (modern) SDM. For self-modifying code "The use of one of these options is not required for programs intended to run on the Pentium or Intel486 processors, but are recommended to ensure compatibility with the P6 and more recent processor families.". For cross-modifying code "The use of this option is not required for programs intended to run on the Intel486 processor, but is recommended to ensure compatibility with the Pentium 4, Intel Xeon, P6 family, and Pentium processors." So I'm not sure there's a problem. I can add an unconditional jump just to make sure. It costs basically nothing on modern CPUs. (Also, CPUID also isn't serializing on 486 according to the table.) --Andy