Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751485AbcLCUd0 (ORCPT ); Sat, 3 Dec 2016 15:33:26 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50634 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750764AbcLCUdV (ORCPT ); Sat, 3 Dec 2016 15:33:21 -0500 Subject: Re: [SPCR] mmio32 iotype access requirements for X-Gene 8250(_dw) UART To: Mark Salter , Duc Dang References: <20161201183350.GF30746@bhelgaas-glaptop.roam.corp.google.com> <6d593615-e97f-8738-42be-1f8f4906d2f4@redhat.com> <175F32B0-C73F-4250-9E60-3CE7409F0B0C@redhat.com> <7fa523de-3fbb-1566-f521-927143f73d1e@redhat.com> <1480785308.4751.41.camel@redhat.com> Cc: Rafael Wysocki , Arnd Bergmann , linux-arm , Linux Kernel Mailing List , patches , Aleksey Makarov , "linux-acpi@vger.kernel.org" , Grant Likely From: Jon Masters Message-ID: Date: Sat, 3 Dec 2016 15:33:15 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.0 MIME-Version: 1.0 In-Reply-To: <1480785308.4751.41.camel@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Sat, 03 Dec 2016 20:33:20 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1357 Lines: 34 Hi Mark, On 12/03/2016 12:15 PM, Mark Salter wrote: > On Sat, 2016-12-03 at 05:06 -0500, Jon Masters wrote: >> There is a broader problem with X-Gene SPCR support. The problem is >> that the 16550 UART in X-Gene requires the 32-bit access quirk (the >> iotype is set to UPIO_MEM32 for the APMC0D08 device). This means >> that when univ8250_console_match runs later, it will compare the >> iotype (MEM32) with the type previously registered with the >> kernel when the earlycon setup the preferred console. > > Linaro has a kernel patch which looks at the bit_width field of the > port address: > > Author: Aleksey Makarov > Date: Thu Apr 28 19:52:38 2016 +0300 > > serial: SPCR: check bit width for the 16550 UART > > The SPCR in 3.06.25 firmware has a bit_width field set to 32 and with the > above patch, I don't need to use console=. But HP firmware on m400 sets > bit width to 8 so that needs a firmware fix to work with above. Indeed, thanks. Graeme also mentioned that last night. I think this a good solution for the moment, but still that it makes sense to have a new 16650 UART type defined in the DBG2 spec for those requiring 32-bit access (to mirror the type D for pl011). I heard back from Microsoft this morning that they're looking. Jon. -- Computer Architect | Sent from my Fedora powered laptop