Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751372AbcLEBem (ORCPT ); Sun, 4 Dec 2016 20:34:42 -0500 Received: from mail.kmu-office.ch ([178.209.48.109]:33145 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751070AbcLEBek (ORCPT ); Sun, 4 Dec 2016 20:34:40 -0500 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Date: Sun, 04 Dec 2016 17:26:58 -0800 From: Stefan Agner To: Shawn Guo Cc: Sascha Hauer , Mark Rutland , devicetree@vger.kernel.org, linux-kernel , robh+dt@kernel.org, Peter Chen , Fabio Estevam , Liu Ying , linux-arm-kernel@lists.infradead.org, Fabio Estevam Subject: Re: [PATCH] ARM: dts: imx7d: fix LCDIF clock assignment In-Reply-To: References: <20161123004204.10851-1-stefan@agner.ch> Message-ID: <7e4829f484f6c4425fc9d01bea1a094f@agner.ch> User-Agent: Roundcube Webmail/1.1.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1093 Lines: 32 Hi Shawn On 2016-11-23 15:02, Fabio Estevam wrote: > On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner wrote: >> The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them >> separately: >> >> Clock Clock Root Description >> apb_clk MAIN_AXI_CLK_ROOT AXI clock >> pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock >> ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock >> >> All of them are switched by a single gate, which is part of the >> IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for >> the AXI bus clock (clock-name "axi") makes sure the gate gets >> enabled when accessing registers. >> >> There seem to be no separate AXI display clock, and the clock is >> optional. Hence remove the dummy clock. >> >> This fixes kernel freezes when starting the X-Server (which >> disables/re-enables the display controller). >> >> Signed-off-by: Stefan Agner > > Reviewed-by: Fabio Estevam Since this fixes a kernel freeze, is there a chance to get this still in 4.9? -- Stefan