Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752198AbcLFK50 (ORCPT ); Tue, 6 Dec 2016 05:57:26 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:36766 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751277AbcLFK5Y (ORCPT ); Tue, 6 Dec 2016 05:57:24 -0500 From: Nicolas Ferre To: Boris BREZILLON , , , , , CC: Alexandre Belloni , Ludovic Desroches , Songjun Wu , , Nicolas Ferre Subject: [RFC PATCH 0/3] clk: at91: audio PLL clock Date: Tue, 6 Dec 2016 11:55:57 +0100 Message-ID: X-Mailer: git-send-email 2.9.0 MIME-Version: 1.0 Content-Type: text/plain X-Brightmail-Tracker: H4sIAAAAAAAAC+NgFvrOosTGxcLF5cOiGznTLcLgxJy2Tl6L+9dOs1jc+7SN0eL6vH3MFgf6+S2+NhlbTJv+jtmBLYAhijUzLym/IoE1403XVtaCa7wV+248Z2pgnMfVxcjFISSwjlFi9fKLrF2MnBxsAroSZyc8YQNJiAhcY5T4fX4BO4jDLPCQUWL9qwfsIFXCAsYSuxeuYgGxWQRUJB79eMIMYvMKWEms/dfMCGJLCMhJNJy/DxUXlDg58wlYPbOAhMTBFy/A4kJAvX3v+9kh6gMlVh8/zAZhO0n8XzkTKm4ncXj6RSjbQeL+/RlwNQe3PoeytSW2v9rHCmHrSGw72M8CYdtK7JkxkQnCdpd48Gg5lO0rMethA1RNlMSp/s+sExjFZiE5dRaSUxcwMq1ilHb28NMNDtN1jXD2MDDTy03OKNDNTczM00vOz93ECImU7B2MZ9r8DzFKcjApifJunXQ+XIgvKT+lMiOxOCO+qDQntfgQowQHj5II76FlQDne4oLE3OLMdJiUDAeHkgTvBZCUYFFqempFWmZOSWoRRPoUo6SUOO89kKQASF9GaR5c7hKjqJQwb9RSoBxPQWpRbmYJRPwWozDHQyYhlrz8vFQpoBMZgECD8RWjOAejkjDvRZBZPJl5JXAnvAK6jgnounW7T4NcV5KIkJJqYFwT7qq+N7ql/fIi329fHH96vEs4tf/nydylmWI2uVoii89+S59xf/6axes8OyMn//A/O2Hf3X+XBMS/lh3hnFFfZGZqrLp52uO27axb2DiyfJmO9Pndn5UlI/xqg3IubwNzg7aajfW/K/apdTYWP9PUvgUsi81YkPptRoaVdIh6TN3b8ncGL5VYijMSDbWYi4oTAeyTqoIKAwAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1706 Lines: 42 This series covers the addition of the Audio PLL clock found on AT91 SoCs like the SAMA5D2. I also added the use of these clocks by the ClassD audi amplifier in both SoC and board DT. The Audio PLL is described in the sama5d2 datasheet chapter "29.8 Audio PLL". Even if "it works" (!), note that I'm not satisfied with the current code and would need some advice from people more accustomed with the CCF and particularly composite audio PLL/clocks like these. For example, I do not take into account the limits of these clocks (as described in the datasheet) and the dependency between the PAD and the PMC child clocks. Thanks in advance for your inputs. Best regards, Nicolas Cyrille Pitchen (2): ARM: dts: at91: sama5d2: add classd nodes ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd Nicolas Ferre (1): clk: at91: add audio pll clock driver .../devicetree/bindings/clock/at91-clock.txt | 10 + arch/arm/boot/dts/at91-sama5d2_xplained.dts | 16 ++ arch/arm/boot/dts/sama5d2.dtsi | 39 +++- arch/arm/mach-at91/Kconfig | 4 + drivers/clk/at91/Makefile | 2 + drivers/clk/at91/clk-audio-pll-pad.c | 238 +++++++++++++++++++ drivers/clk/at91/clk-audio-pll-pmc.c | 184 +++++++++++++++ drivers/clk/at91/clk-audio-pll.c | 253 +++++++++++++++++++++ include/linux/clk/at91_pmc.h | 25 ++ 9 files changed, 770 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c create mode 100644 drivers/clk/at91/clk-audio-pll.c -- 2.9.0