Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753362AbcLHLfj (ORCPT ); Thu, 8 Dec 2016 06:35:39 -0500 Received: from foss.arm.com ([217.140.101.70]:58762 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751729AbcLHLfi (ORCPT ); Thu, 8 Dec 2016 06:35:38 -0500 Subject: Re: [PATCH] arm64: Work around Falkor erratum 1009 To: Will Deacon , Christopher Covington References: <20161207200028.4420-1-cov@codeaurora.org> <20161207200431.4587-1-cov@codeaurora.org> <20161208112042.GB706@arm.com> Cc: Catalin Marinas , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Christoffer Dall , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Shanker Donthineni From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Thu, 8 Dec 2016 11:35:34 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Icedove/45.2.0 MIME-Version: 1.0 In-Reply-To: <20161208112042.GB706@arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2483 Lines: 61 On 08/12/16 11:20, Will Deacon wrote: > On Wed, Dec 07, 2016 at 03:04:31PM -0500, Christopher Covington wrote: >> From: Shanker Donthineni >> >> During a TLB invalidate sequence targeting the inner shareable >> domain, Falkor may prematurely complete the DSB before all loads >> and stores using the old translation are observed; instruction >> fetches are not subject to the conditions of this erratum. >> >> Signed-off-by: Shanker Donthineni >> Signed-off-by: Christopher Covington >> --- >> arch/arm64/Kconfig | 10 +++++++++ >> arch/arm64/include/asm/cpucaps.h | 3 ++- >> arch/arm64/include/asm/tlbflush.h | 43 +++++++++++++++++++++++++++++++++++++++ >> arch/arm64/kernel/cpu_errata.c | 7 +++++++ >> arch/arm64/kvm/hyp/tlb.c | 39 ++++++++++++++++++++++++++++++----- >> 5 files changed, 96 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 1004a3d..125440f 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -485,6 +485,16 @@ config QCOM_FALKOR_ERRATUM_E1003 >> >> If unsure, say Y. >> >> +config QCOM_FALKOR_ERRATUM_E1009 >> + bool "Falkor E1009: Prematurely complete a DSB after a TLBI" >> + default y >> + help >> + Falkor CPU may prematurely complete a DSB following a TLBI xxIS >> + invalidate maintenance operations. Repeat the TLBI operation one >> + more time to fix the issue. >> + >> + If unsure, say Y. > > Call me perverse, but I like this workaround. People often tend to screw > up TLBI and DVM sync, but the IPI-based workaround is horribly invasive > and fragile. Simply repeating the operation tends to be enough to make > the chance of failure small enough to be acceptable. > >> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h >> index cb6a8c2..5357d7f 100644 >> --- a/arch/arm64/include/asm/cpucaps.h >> +++ b/arch/arm64/include/asm/cpucaps.h >> @@ -35,7 +35,8 @@ >> #define ARM64_HYP_OFFSET_LOW 14 >> #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 >> #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 16 >> +#define ARM64_WORKAROUND_QCOM_FALKOR_E1009 17 > > Could you rename this to something like ARM64_WORKAROUND_REPEAT_TLBI, so > that it could potentially be used by others? And add a parameter to it so that we can generate multiple TLBIs, depending on the level of brokenness? ;-) M. -- Jazz is not dead. It just smells funny...