Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753409AbcLHMR5 (ORCPT ); Thu, 8 Dec 2016 07:17:57 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:40230 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752139AbcLHMR4 (ORCPT ); Thu, 8 Dec 2016 07:17:56 -0500 Subject: Re: Tearing down DMA transfer setup after DMA client has finished To: Geert Uytterhoeven , Mans Rullgard Cc: Vinod Koul , Russell King , dmaengine@vger.kernel.org, Linus Walleij , Dan Williams , LKML , Linux ARM , Jon Mason , Mark Brown , Lars-Peter Clausen , Lee Jones , Laurent Pinchart , Arnd Bergmann , Maxime Ripard , Dave Jiang , Peter Ujfalusi , Bartlomiej Zolnierkiewicz , Sebastian Frias , Thibaud Cornic References: <58356EA8.2010806@free.fr> <20161125045549.GC2698@localhost> <092f44ee-4560-be17-25f7-00948dba3cfa@free.fr> <20fc9020-7278-bc2f-2a8d-43aff5cabff8@free.fr> <20161206051222.GQ6408@localhost> <5846B237.8060409@free.fr> <20161207164341.GX6408@localhost> <20161208103921.GC6408@localhost> <91b0d10c-1bc2-c3e1-4088-f4ad9adcd6c0@free.fr> From: Mason Message-ID: <964975b8-5c00-9726-20e4-a1e801ce28d6@free.fr> Date: Thu, 8 Dec 2016 13:17:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:50.0) Gecko/20100101 Firefox/50.0 SeaMonkey/2.47 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Language: Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 713 Lines: 21 On 08/12/2016 13:03, Geert Uytterhoeven wrote: > Måns Rullgård wrote: > >> Geert Uytterhoeven writes: >> >>> Can you fall back to PIO if requesting a channel fails? >> >> Why are we debating this nonsense? There is an easy fix that doesn't >> require changing the semantics of existing functions or falling back to >> slow pio. > > You still want to fall back to PIO if the DMA engine is not available > at all (e.g. DMA engine driver not compiled in, or module not loaded). FWIW, the ECC engine is tied to the DMA engine. So PIO means not only taking a hit from tying up the CPU for a slooow transfer, but also a huge hit if ECC must be computed in SW. (A 100x perf degradation is not unlikely.) Regards.