Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932334AbcLHNji convert rfc822-to-8bit (ORCPT ); Thu, 8 Dec 2016 08:39:38 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:42034 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751845AbcLHNjh (ORCPT ); Thu, 8 Dec 2016 08:39:37 -0500 From: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= To: Mason Cc: Geert Uytterhoeven , Vinod Koul , Russell King , dmaengine@vger.kernel.org, Linus Walleij , Dan Williams , LKML , Linux ARM , Jon Mason , Mark Brown , Lars-Peter Clausen , Lee Jones , Laurent Pinchart , Arnd Bergmann , Maxime Ripard , Dave Jiang , Peter Ujfalusi , Bartlomiej Zolnierkiewicz , Sebastian Frias , Thibaud Cornic , Thomas Gambier Subject: Re: Tearing down DMA transfer setup after DMA client has finished References: <58356EA8.2010806@free.fr> <20161125045549.GC2698@localhost> <092f44ee-4560-be17-25f7-00948dba3cfa@free.fr> <20fc9020-7278-bc2f-2a8d-43aff5cabff8@free.fr> <20161206051222.GQ6408@localhost> <5846B237.8060409@free.fr> <20161207164341.GX6408@localhost> <20161208103921.GC6408@localhost> <68bbe77a-c991-4e64-c189-fafbcda8e7ae@free.fr> Date: Thu, 08 Dec 2016 13:39:31 +0000 In-Reply-To: <68bbe77a-c991-4e64-c189-fafbcda8e7ae@free.fr> (Mason's message of "Thu, 8 Dec 2016 14:29:17 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1882 Lines: 53 Mason writes: > On 08/12/2016 13:44, M?ns Rullg?rd wrote: > >> Mason writes: >> >>> On 08/12/2016 13:20, M?ns Rullg?rd wrote: >>> >>>> The only problem we have is that nobody envisioned hardware where the >>>> dma engine indicates completion slightly too soon. I suspect there's a >>>> fifo or such somewhere, and the interrupt is triggered when the last >>>> byte has been placed in the fifo rather than when it has been removed >>>> which would have been more correct. >>> >>> As I (tried to) explain here: >>> https://marc.info/?l=dmaengine&m=148007808418242&w=2 >>> >>> A *read* MBUS agent raises its IRQ when it is safe for the memory >>> to be overwritten (i.e. every byte has been pushed into the pipe). >>> >>> A *write* MBUS agent raises its IRQ when it is safe for another >>> agent to read any one of the transferred bytes. >>> >>> The issue comes from the fact that, for a memory-to-device transfer, >>> the system will receive the read agent's IRQ, but most devices >>> (NFC, SATA) don't have an IRQ line to signal that their part of the >>> operation is complete. >> >> SATA does, actually. Nevertheless, it's an unusual design. > > Thanks, I was mistaken about the SATA controller. > > On tango3 (and also tango4, I assume) > > IRQ 41 = Serial ATA #0 > IRQ 42 = Serial ATA DMA #0 > IRQ 54 = Serial ATA #1 > IRQ 55 = Serial ATA DMA #1 > > But in the end, whether there is a device interrupt (SATA) > or not (NFC), for a memory-to-device transfer, the DMA > driver will get the read agent notification (which should > be ignored) and the client driver should either spin until > idle (NFC) or wait for its completion IRQ (SATA). > > Correct? Yes, and when the client device is finished, the driver needs to signal this to the dma driver so it can reuse the channel. It's this last piece that's missing. -- M?ns Rullg?rd