Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933187AbcLIFg1 (ORCPT ); Fri, 9 Dec 2016 00:36:27 -0500 Received: from b-painless.mh.aa.net.uk ([81.187.30.52]:40279 "EHLO b-painless.mh.aa.net.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932371AbcLIFgZ (ORCPT ); Fri, 9 Dec 2016 00:36:25 -0500 From: Joel Holdsworth To: atull@opensource.altera.com, moritz.fischer@ettus.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, marex@denx.de Cc: Joel Holdsworth Subject: [PATCH v9 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager Date: Thu, 8 Dec 2016 22:35:48 -0700 Message-Id: <1481261749-15301-2-git-send-email-joel@airwebreathe.org.uk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1481261749-15301-1-git-send-email-joel@airwebreathe.org.uk> References: <1481261749-15301-1-git-send-email-joel@airwebreathe.org.uk> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1617 Lines: 42 This adds documentation of the device tree bindings of the Lattice iCE40 FPGA driver for the FPGA manager framework. Signed-off-by: Joel Holdsworth Acked-by: Rob Herring Acked-by: Alan Tull Acked-by: Moritz Fischer Acked-by: Marek Vasut --- .../bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt new file mode 100644 index 0000000..7e7a78b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt @@ -0,0 +1,21 @@ +Lattice iCE40 FPGA Manager + +Required properties: +- compatible: Should contain "lattice,ice40-fpga-mgr" +- reg: SPI chip select +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) +- cdone-gpios: GPIO input connected to CDONE pin +- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note + that unless the GPIO is held low during startup, the + FPGA will enter Master SPI mode and drive SCK with a + clock signal potentially jamming other devices on the + bus until the firmware is loaded. + +Example: + ice40: ice40@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <1000000>; + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; -- 2.7.4