Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753553AbcLISJP convert rfc822-to-8bit (ORCPT ); Fri, 9 Dec 2016 13:09:15 -0500 Received: from mga11.intel.com ([192.55.52.93]:30766 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752200AbcLISJN (ORCPT ); Fri, 9 Dec 2016 13:09:13 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,324,1477983600"; d="scan'208";a="796223895" From: "Tirdea, Irina" To: Stephen Boyd CC: "linux-clk@vger.kernel.org" , "x86@kernel.org" , "platform-driver-x86@vger.kernel.org" , Darren Hart , Thomas Gleixner , Michael Turquette , Ingo Molnar , "H. Peter Anvin" , "alsa-devel@alsa-project.org" , Mark Brown , Takashi Iwai , "Bossart, Pierre-louis" , "Rafael J. Wysocki" , Len Brown , "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Pierre-Louis Bossart" Subject: RE: [PATCH v5 2/2] clk: x86: Add Atom PMC platform clocks Thread-Topic: [PATCH v5 2/2] clk: x86: Add Atom PMC platform clocks Thread-Index: AQHSUKDCGqLIpoe54Eya1DNi+aiZp6D+xDSAgAEooVA= Date: Fri, 9 Dec 2016 18:09:03 +0000 Deferred-Delivery: Fri, 9 Dec 2016 18:09:00 +0000 Message-ID: <1F3AC3675D538145B1661F571FE1805F2F3B77FA@irsmsx105.ger.corp.intel.com> References: <1481125406-29097-1-git-send-email-irina.tirdea@intel.com> <1481125406-29097-3-git-send-email-irina.tirdea@intel.com> <20161209002523.GC5423@codeaurora.org> In-Reply-To: <20161209002523.GC5423@codeaurora.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGU4ZGJkY2MtN2E1NC00YjcwLWI1NTMtNDUxN2ExMzFhYThiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImFEK0tQWFRMQmQ0RzY3UnZMNXRmb05oTlpZenR1WFZYU1A0cmViVnZ3NkE9In0= x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1244 Lines: 32 On 2016-12-09 02:25, Stephen Boyd wrote: > On 12/07, Irina Tirdea wrote: >> The BayTrail and CherryTrail platforms provide platform clocks >> through their Power Management Controller (PMC). >> >> The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0]) with a >> frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail >> an a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks >> are available for general system use, where appropriate, and each >> have Control & Frequency register fields associated with them. >> >> For example, the usage for platform clocks suggested in the datasheet >> is the following: >> PLT_CLK[2:0] - Camera >> PLT_CLK[3] - Audio Codec >> PLT_CLK[4] - >> PLT_CLK[5] - COMMs >> Signed-off-by: Irina Tirdea Signed-off-by: >> Pierre-Louis Bossart --- >> drivers/clk/x86/Makefile | 1 + >> drivers/clk/x86/clk-byt-plt.c | 380 > ++++++++++++++++++++++++++ > > Is it possible to split the clk part from the platform part? I'd > like to merge just the clk part if possible into the clk tree. > It would be great to have the clk part merged. I'll put the code in a separate patch. Thanks, Irina