Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752487AbcLKBTO (ORCPT ); Sat, 10 Dec 2016 20:19:14 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35055 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751639AbcLKBTM (ORCPT ); Sat, 10 Dec 2016 20:19:12 -0500 Date: Sat, 10 Dec 2016 17:19:09 -0800 From: Yinghai Lu To: Bjorn Helgaas Cc: Vaibhav Shankar , bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, venkateswarlu.v.vinjamuri@intel.com Subject: Re: [PATCH] PCI: pciehp: Optimize PCIe root resume time Message-ID: <20161211011908.GA10954@linux-siqj.site> References: <1481323406-12865-1-git-send-email-vaibhav.shankar@intel.com> <20161210002744.GB8381@bhelgaas-glaptop.roam.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161210002744.GB8381@bhelgaas-glaptop.roam.corp.google.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2527 Lines: 75 On Fri, Dec 09, 2016 at 06:27:44PM -0600, Bjorn Helgaas wrote: > [+cc Yinghai, author of 2f5d8e4ff947] > > On Fri, Dec 09, 2016 at 02:43:26PM -0800, Vaibhav Shankar wrote: > > On Apollolake platforms, PCIe rootport takes a long time to resume > > from S3. With 100ms delay before read pci conf, rootport takes > > ~200ms during resume. > > > > commit 2f5d8e4ff947 ("PCI: pciehp: replace unconditional sleep with > > config space access check") is the one that added the 100ms delay > > before reading pci conf. > > > > This patch removes the 100ms delay.By removing the delay, the > > PCIe root port takes ~16ms during resume. As per PCIe spec, we > > only require 1000ms delay. This delay is provide by > > pci_bus_check_dev() function. > > > > Signed-off-by: Vaibhav Shankar > > --- > > drivers/pci/hotplug/pciehp_hpc.c | 2 -- > > 1 file changed, 2 deletions(-) > > > > diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c > > index 5c24e93..08357e7 100644 > > --- a/drivers/pci/hotplug/pciehp_hpc.c > > +++ b/drivers/pci/hotplug/pciehp_hpc.c > > @@ -311,8 +311,6 @@ int pciehp_check_link_status(struct controller *ctrl) > > else > > msleep(1000); > > > > - /* wait 100ms before read pci conf, and try in 1s */ > > - msleep(100); > > found = pci_bus_check_dev(ctrl->pcie->port->subordinate, > > PCI_DEVFN(0, 0)); that msleep(100) is from that commit: - /* - * If the port supports Link speeds greater than 5.0 GT/s, we - * must wait for 100 ms after Link training completes before - * sending configuration request. - */ - if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT) - msleep(100); so we should put the checking back. diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 026830a..1b0fc0b 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -311,8 +311,15 @@ int pciehp_check_link_status(struct controller *ctrl) else msleep(1000); - /* wait 100ms before read pci conf, and try in 1s */ - msleep(100); + /* + * If the port supports Link speeds greater than 5.0 GT/s, we + * must wait for 100 ms after Link training completes before + * sending configuration request. + */ + if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT) + msleep(100); + + /* try in 1s */ found = pci_bus_check_dev(ctrl->pcie->port->subordinate, PCI_DEVFN(0, 0)); Thanks Yinghai