Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932578AbcLMED5 convert rfc822-to-8bit (ORCPT ); Mon, 12 Dec 2016 23:03:57 -0500 Received: from mga05.intel.com ([192.55.52.43]:22136 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932396AbcLMEDz (ORCPT ); Mon, 12 Dec 2016 23:03:55 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,340,1477983600"; d="scan'208";a="797329296" From: "Li, Liang Z" To: Paolo Bonzini , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" Subject: RE: [RFC PATCH 0/4] KVM: Emulate UMIP (or almost do so) Thread-Topic: [RFC PATCH 0/4] KVM: Emulate UMIP (or almost do so) Thread-Index: AQHR3HKfSivFw1UXu020PWBMQJl3X6EGJ3Hg Date: Tue, 13 Dec 2016 04:03:47 +0000 Message-ID: References: <1468351223-3250-1-git-send-email-pbonzini@redhat.com> In-Reply-To: <1468351223-3250-1-git-send-email-pbonzini@redhat.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWI3NjI0MTItODg4YS00YTZiLTgwYTItMjZhYTI2NjcyMTkyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IkFWZzc4QkhQb1wvZXJHZkhRTXVDVHY1U1I2cFE1WkYzNlwvVThQVHRCUE1xST0ifQ== x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 978 Lines: 24 > UMIP (User-Mode Instruction Prevention) is a feature of future Intel > processors (Cannonlake?) that blocks SLDT, SGDT, STR, SIDT and SMSW from > user-mode processes. > > The idea here is to use virtualization intercepts to emulate UMIP; it slows > down the instructions when they're executed in ring 0, but they are really > never executed in practice. On AMD systems it's possible to emulate it > entirely; instead on Intel systems it's *almost* possible to emulate it, > because SMSW doesn't cause a vmexit, and hence SMSW will not fault. > > This patch series provides the infrastructure and implements it on Intel. I > tested it through kvm-unit-tests. > > Still I think the idea is interesting, even if it's buggy for current Intel > processors. Any opinions? Hi Paolo, We intended to enable UMIP for KVM and found you had already worked on it. Do you have any plan for the following patch set? It's there anything else you expect us help to do? Thanks! Liang