Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932672AbcLMIsy (ORCPT ); Tue, 13 Dec 2016 03:48:54 -0500 Received: from regular1.263xmail.com ([211.150.99.132]:33825 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932642AbcLMIst (ORCPT ); Tue, 13 Dec 2016 03:48:49 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhangqing@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Elaine Zhang To: heiko@sntech.de, mturquette@baylibre.com, sboyd@codeaurora.org, xf@rock-chips.com Cc: robh+dt@kernel.org, mark.rutland@arm.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, cl@rock-chips.com, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Elaine Zhang Subject: [PATCH v1 3/3] clk: rockchip: add new pll-type for rk3328 and similar socs Date: Tue, 13 Dec 2016 16:47:49 +0800 Message-Id: <1481618869-1239-4-git-send-email-zhangqing@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481618869-1239-1-git-send-email-zhangqing@rock-chips.com> References: <1481618869-1239-1-git-send-email-zhangqing@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1793 Lines: 58 The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask,there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-pll.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 6ed605776abd..9650c75f61d1 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -29,6 +29,7 @@ #define PLL_MODE_SLOW 0x0 #define PLL_MODE_NORM 0x1 #define PLL_MODE_DEEP 0x2 +#define PLL_RK3328_MODE_MASK 0x1 struct rockchip_clk_pll { struct clk_hw hw; @@ -865,13 +866,17 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, pll_mux = &pll->pll_mux; pll_mux->reg = ctx->reg_base + mode_offset; pll_mux->shift = mode_shift; - pll_mux->mask = PLL_MODE_MASK; + if (pll_type == pll_rk3328) + pll_mux->mask = PLL_RK3328_MODE_MASK; + else + pll_mux->mask = PLL_MODE_MASK; pll_mux->flags = 0; pll_mux->lock = &ctx->lock; pll_mux->hw.init = &init; if (pll_type == pll_rk3036 || pll_type == pll_rk3066 || + pll_type == pll_rk3328 || pll_type == pll_rk3399) pll_mux->flags |= CLK_MUX_HIWORD_MASK; @@ -929,6 +934,12 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, else init.ops = &rockchip_rk3066_pll_clk_ops; break; + case pll_rk3328: + if (!pll->rate_table || IS_ERR(ctx->grf)) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3036_pll_clk_ops; + break; case pll_rk3399: if (!pll->rate_table) init.ops = &rockchip_rk3399_pll_clk_norate_ops; -- 1.9.1