Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932749AbcLMKCh (ORCPT ); Tue, 13 Dec 2016 05:02:37 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51117 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932469AbcLMKCd (ORCPT ); Tue, 13 Dec 2016 05:02:33 -0500 Subject: Re: [PATCH v6 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC To: "M'boumba Cedric Madianga" , , , , , , , , , , References: <1481559342-6106-1-git-send-email-cedric.madianga@gmail.com> <1481559342-6106-4-git-send-email-cedric.madianga@gmail.com> From: Alexandre Torgue Message-ID: Date: Tue, 13 Dec 2016 11:01:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1481559342-6106-4-git-send-email-cedric.madianga@gmail.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-12-13_07:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1544 Lines: 64 Hi Cedric, On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote: > Signed-off-by: Patrice Chotard > Signed-off-by: M'boumba Cedric Madianga Please Add a commit message. > --- > arch/arm/boot/dts/stm32f429.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi > index 7de52ee..cbdece7 100644 > --- a/arch/arm/boot/dts/stm32f429.dtsi > +++ b/arch/arm/boot/dts/stm32f429.dtsi > @@ -48,6 +48,7 @@ > #include "skeleton.dtsi" > #include "armv7-m.dtsi" > #include > +#include > > / { > clocks { > @@ -337,6 +338,16 @@ > slew-rate = <2>; > }; > }; > + > + i2c1_pins_b: i2c1@0 { > + pins1 { > + pinmux = ; > + drive-open-drain; > + }; > + pins2 { > + pinmux = ; > + }; > + }; > }; > > rcc: rcc@40023810 { > @@ -409,6 +420,18 @@ > interrupts = <80>; > clocks = <&rcc 0 38>; > }; > + > + i2c1: i2c@40005400 { Can you check the order on device node please ? (should follow base@) > + compatible = "st,stm32f4-i2c"; > + reg = <0x40005400 0x400>; > + interrupts = <31>, > + <32>; > + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; > + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > }; > }; > >