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Date: Tue, 13 Dec 2016 13:14:17 -0000
From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Peter Zijlstra <peterz@infradead.org>,
        Borislav Petkov <bp@alien8.de>,
        Bruce Schlobohm <bruce.schlobohm@intel.com>,
        Roland Scheidegger <rscheidegger_lists@hispeed.ch>,
        Kevin Stanton <kevin.b.stanton@intel.com>,
        Allen Hung <allen_hung@dell.com>
Subject: [patch 0/2] tsc/adjust: Cure suspend/resume issues and prevent TSC
 deadline timer irq storm
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Roland reported interesting TSC ADJUST register wreckage on his DELL
machine, which seems to populate that MSR with a random number generator.

Deeper investagation into fixing this wreckage unearthed another special
feature which is designed by Intel: Negative TSC adjuste values cause
interrupt storms on the TSC deadline timer. Further details in patch 2/2

Thanks

	tglx