Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934653AbcLOA3H (ORCPT ); Wed, 14 Dec 2016 19:29:07 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:34736 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933628AbcLOA3E (ORCPT ); Wed, 14 Dec 2016 19:29:04 -0500 MIME-Version: 1.0 In-Reply-To: <1481710301-1454-2-git-send-email-zhengxing@rock-chips.com> References: <1481710301-1454-1-git-send-email-zhengxing@rock-chips.com> <1481710301-1454-2-git-send-email-zhengxing@rock-chips.com> From: Doug Anderson Date: Wed, 14 Dec 2016 16:27:49 -0800 Message-ID: Subject: Re: [PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs To: Xing Zheng Cc: "open list:ARM/Rockchip SoC..." , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Rob Herring , Mark Rutland , Lin Huang , Chris Zhong , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 969 Lines: 27 Hi, On Wed, Dec 14, 2016 at 2:11 AM, Xing Zheng wrote: > This patch add two clock IDs for the usb phy 480m source clocks. > > Signed-off-by: Xing Zheng > --- > > include/dt-bindings/clock/rk3399-cru.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h > index 220a60f..224daf7 100644 > --- a/include/dt-bindings/clock/rk3399-cru.h > +++ b/include/dt-bindings/clock/rk3399-cru.h > @@ -132,6 +132,8 @@ > #define SCLK_RMII_SRC 166 > #define SCLK_PCIEPHY_REF100M 167 > #define SCLK_DDRC 168 > +#define SCLK_USBPHY0_480M_SRC 169 > +#define SCLK_USBPHY1_480M_SRC 170 As mentioned in the dts patch, I don't think you need these since I'm under the impression that nobody gets this clock. I think the USB Controller get the ungated version of this clock. -Doug