Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759571AbcLPIvO (ORCPT ); Fri, 16 Dec 2016 03:51:14 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:48863 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756943AbcLPIvD (ORCPT ); Fri, 16 Dec 2016 03:51:03 -0500 Date: Fri, 16 Dec 2016 09:47:36 +0100 (CET) From: Thomas Gleixner To: Andy Lutomirski cc: LKML , X86 ML , Peter Zijlstra , Kyle Huey , Andy Lutomirski Subject: Re: [patch 2/3] x86/process: Optimize TIF_BLOCKSTEP switch In-Reply-To: Message-ID: References: <20161215162648.061449202@linutronix.de> <20161215164240.813682510@linutronix.de> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1174 Lines: 39 On Thu, 15 Dec 2016, Andy Lutomirski wrote: > On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner wrote: > > +static inline void toggle_debugctlmsr(unsigned long mask) > > +{ > > + unsigned long msrval; > > + > > +#ifndef CONFIG_X86_DEBUGCTLMSR > > + if (boot_cpu_data.x86 < 6) > > + return; > > +#endif > > + rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval); > > + wrmsrl(MSR_IA32_DEBUGCTLMSR, msrval ^ mask); > > +} > > + > > This scares me. If the MSR ever gets out of sync with the TI flag, > this will malfunction. And IIRC the MSR is highly magical and the CPU > clears it all by itself under a variety of not-so-well documented > circumstances. If that is true, then the code today is broken as well, when the flag has been cleared and both prev and next have the flag set. Then it won't be updated for the next task. The we should not use the TIF flag and store a debugmask in thread info and do: if (prev->debugmask || next->debugmask) { if (static_cpu_has(X86_FEATURE_BLOCKSTEP)) { rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval); msrval &= DEBUGCTLMSR_BTF; msrval |= next->debugmask; } } Thanks, tglx