Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758251AbcLQBUd convert rfc822-to-8bit (ORCPT ); Fri, 16 Dec 2016 20:20:33 -0500 Received: from gloria.sntech.de ([95.129.55.99]:52231 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752360AbcLQBUc (ORCPT ); Fri, 16 Dec 2016 20:20:32 -0500 From: Heiko Stuebner To: Xing Zheng Cc: Doug Anderson , Frank Wang , Brian Norris , William wu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Caesar Wang , Jianqun Xu , Elaine Zhang , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Dmitry Torokhov , Tao Huang , "open list:ARM/Rockchip SoC..." , "daniel.meng" , Kever Yang , =?utf-8?B?6YOR5YW0?= Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399 Date: Sat, 17 Dec 2016 02:20:22 +0100 Message-ID: <9948170.UXsXzrYPRK@phil> User-Agent: KMail/5.2.3 (Linux/4.8.0-1-amd64; KDE/5.27.0; x86_64; ; ) In-Reply-To: <5853903D.8030605@rock-chips.com> References: <1481710301-1454-1-git-send-email-zhengxing@rock-chips.com> <2526685.VC5cUs58On@phil> <5853903D.8030605@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2521 Lines: 66 Am Freitag, 16. Dezember 2016, 14:57:01 CET schrieb Xing Zheng: > Hi Heiko, Doug, > > On 2016年12月16日 02:18, Heiko Stuebner wrote: > > Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson: > >> I still need to digest all of the things that were added to this > >> thread overnight, but nothing I've seen so far indicates that you need > >> the post-gated clock. AKA I still think you need to redo your patch > >> > >> to replace: > >> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > >> > >> <&cru SCLK_USBPHY0_480M_SRC>; > >> > >> with: > >> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > >> > >> <&u2phy0>; > >> > >> Can you please comment on that? > > > > Also, with the change, the ehci will keep the clock (and thus the phy) > > always on. Does the phy-autosuspend even save anything now? > > > > In any case, could we make the clock-names entry sound nicer than > > usbphy0_480m please? bindings/usb/atmel-usb.txt calls its UTMI clock > > simply "usb_clk", but something like "utmi" should also work. > > While at it you could also fix up the other clock names to something like > > "host" and "arbiter" or so?. > > > > > > Heiko > > The usbphy related clock tress like this: > > > Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only > enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK. > > And the naming style of the "hclk_host0" keep the name "hclk_host0" on > the clcok tree diagram: > > > Therefore, could we rename the clock name like this: > ---- > for usb_host0_ehci and usb_host0_ohci: > clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, > <&cru SCLK_U2PHY0>; > clock-names = "hclk_host0", "hclk_host0_arb", > "sclk_u2phy0"; > > for usb_host1_ehci and usb_host1_ohci: > clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, > <&cru SCLK_U2PHY1>; > clock-names = "hclk_host1", "hclk_host1_arb", > "sclk_u2phy1"; > ---- > > BTW, the "arb" is an abbreviation for arbiter. clock-naming wise, the clock names in devicetree bindings should always describe the clock in the context of the peripheral, not the hosts clock-tree. So if the clock supplies the "arbiter" part, the clock-name should be called "arbiter". Same for "utmi" and the host clock that could be named "usbhost" or just "host" in the clock-names property.