Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933169AbcLSLQx (ORCPT ); Mon, 19 Dec 2016 06:16:53 -0500 Received: from mail-it0-f65.google.com ([209.85.214.65]:36403 "EHLO mail-it0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932352AbcLSLQv (ORCPT ); Mon, 19 Dec 2016 06:16:51 -0500 MIME-Version: 1.0 In-Reply-To: <1482039234-21335-2-git-send-email-joel@airwebreathe.org.uk> References: <1482039234-21335-1-git-send-email-joel@airwebreathe.org.uk> <1482039234-21335-2-git-send-email-joel@airwebreathe.org.uk> From: Geert Uytterhoeven Date: Mon, 19 Dec 2016 12:16:50 +0100 X-Google-Sender-Auth: RIaykcnfbAkvWjNdqyXmTXGCEIM Message-ID: Subject: Re: [PATCH v10 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager To: Joel Holdsworth Cc: atull@opensource.altera.com, Moritz Fischer , Rob Herring , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , linux-spi , Marek Vasut , linux-fpga@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2004 Lines: 52 Hi Joel, On Sun, Dec 18, 2016 at 6:33 AM, Joel Holdsworth wrote: > This adds documentation of the device tree bindings of the Lattice iCE40 > FPGA driver for the FPGA manager framework. > > Signed-off-by: Joel Holdsworth > Acked-by: Rob Herring > Acked-by: Alan Tull > Acked-by: Moritz Fischer > Acked-by: Marek Vasut > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt > @@ -0,0 +1,21 @@ > +Lattice iCE40 FPGA Manager > + > +Required properties: > +- compatible: Should contain "lattice,ice40-fpga-mgr" > +- reg: SPI chip select > +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) > +- cdone-gpios: GPIO input connected to CDONE pin > +- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note > + that unless the GPIO is held low during startup, the > + FPGA will enter Master SPI mode and drive SCK with a > + clock signal potentially jamming other devices on the > + bus until the firmware is loaded. > + > +Example: > + ice40: ice40@0 { As per ePAPR, node names should be generic names, e.g. "fpga@0". Sorry for not noticing before. > + compatible = "lattice,ice40-fpga-mgr"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; > + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds