Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762038AbcLSRA1 (ORCPT ); Mon, 19 Dec 2016 12:00:27 -0500 Received: from eusmtp01.atmel.com ([212.144.249.243]:47790 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754342AbcLSRA0 (ORCPT ); Mon, 19 Dec 2016 12:00:26 -0500 Subject: Re: [PATCH v4 4/8] mtd: spi-nor: add support of SPI protocols like SPI 1-2-2 and SPI 1-4-4 To: "Krzeminski, Marcin (Nokia - PL/Wroclaw)" , "'computersforpeace@gmail.com'" , "'marek.vasut@gmail.com'" , "'boris.brezillon@free-electrons.com'" , "'richard@nod.at'" , "'linux-mtd@lists.infradead.org'" References: <9adeee98798f3ba9bb01f86e1bd1a3543643a2ec.1479736401.git.cyrille.pitchen@atmel.com> CC: "'nicolas.ferre@atmel.com'" , "'linux-kernel@vger.kernel.org'" From: Cyrille Pitchen Message-ID: <8f70a04f-33f8-c703-0836-db1d3e07aca5@atmel.com> Date: Mon, 19 Dec 2016 18:00:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.145.133.18] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4014 Lines: 98 Le 16/12/2016 ? 14:47, Krzeminski, Marcin (Nokia - PL/Wroclaw) a ?crit : >> -----Original Message----- >> From: Krzeminski, Marcin (Nokia - PL/Wroclaw) >> Sent: Tuesday, December 13, 2016 10:46 AM >> To: Cyrille Pitchen ; >> computersforpeace@gmail.com; marek.vasut@gmail.com; >> boris.brezillon@free-electrons.com; richard@nod.at; linux- >> mtd@lists.infradead.org >> Cc: nicolas.ferre@atmel.com; linux-kernel@vger.kernel.org >> Subject: RE: [PATCH v4 4/8] mtd: spi-nor: add support of SPI protocols like SPI >> 1-2-2 and SPI 1-4-4 >> >> Cyrille, >> >>> -----Original Message----- >>> From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On >>> Behalf Of Cyrille Pitchen >>> Sent: Monday, November 21, 2016 3:16 PM >>> To: computersforpeace@gmail.com; marek.vasut@gmail.com; >>> boris.brezillon@free-electrons.com; richard@nod.at; linux- >>> mtd@lists.infradead.org >>> Cc: Cyrille Pitchen ; >>> nicolas.ferre@atmel.com; linux-kernel@vger.kernel.org >>> Subject: [PATCH v4 4/8] mtd: spi-nor: add support of SPI protocols >>> like SPI 1- >>> 2-2 and SPI 1-4-4 >>> >>> This patch changes the prototype of spi_nor_scan(): its 3rd parameter >>> is replaced by a const struct spi_nor_modes pointer, which tells the >>> spi-nor framework about which SPI protocols are supported by the SPI >> controller. >>> >>> Besides, this patch also introduces a new >>> spi_nor_basic_flash_parameter structure telling the spi-nor framework >>> about the SPI protocols supported by the SPI memory and the needed op >> codes to use these SPI protocols. >>> >>> Currently the struct spi_nor_basic_flash_parameter is filled with >>> legacy values but a later patch will allow to fill it dynamically by >>> reading the >>> JESD216 Serial Flash Discoverable Parameter (SFDP) tables from the SPI >>> memory. >>> >>> With both structures, the spi-nor framework can now compute the best >>> match between SPI protocols supported by both the (Q)SPI memory and >>> controller hence selecting the relevant op codes for (Fast) Read, Page >>> Program and Sector Erase operations. >>> >>> The spi_nor_basic_flash_parameter structure also provides the spi-nor >>> framework with the number of dummy cycles to be used with each Fast >>> Read commands and the erase block size associated to the erase block >>> op codes. >>> >>> Finally the spi_nor_basic_flash_parameter structure, through the >>> optional >>> .enable_quad_io() hook, tells the spi-nor framework how to set the >>> Quad Enable (QE) bit of the QSPI memory to enable its Quad SPI features. >>> >>> Signed-off-by: Cyrille Pitchen >>> --- >>> drivers/mtd/devices/m25p80.c | 17 ++- >>> drivers/mtd/spi-nor/atmel-quadspi.c | 83 ++++++---- >>> drivers/mtd/spi-nor/cadence-quadspi.c | 18 ++- >>> drivers/mtd/spi-nor/fsl-quadspi.c | 8 +- >>> drivers/mtd/spi-nor/hisi-sfc.c | 32 +++- >>> drivers/mtd/spi-nor/mtk-quadspi.c | 16 +- >>> drivers/mtd/spi-nor/nxp-spifi.c | 21 +-- >>> drivers/mtd/spi-nor/spi-nor.c | 280 >> +++++++++++++++++++++++++++- >>> ------ [...] >>> +static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, >>> + const struct spi_nor_basic_flash_parameter >>> *params, >>> + const struct spi_nor_modes *modes) >>> { >>> + bool enable_quad_io; >>> + u32 rd_modes, wr_modes, mask; >>> + const struct spi_nor_erase_type *erase_type = NULL; >>> + const struct spi_nor_read *read; >>> + int rd_pindex, wr_pindex, i, err = 0; >>> + u8 erase_size = SNOR_ERASE_64K; >> >> Erase size could be configurable, then user can chose best sector size that >> match his use case on multi-sized flash. >> >>> + >>> + /* 2-2-2 or 4-4-4 modes are not supported yet. */ >>> + mask = (SNOR_MODE_2_2_2 | SNOR_MODE_4_4_4); > IMHO could be nice to put a warning here :) > Then maybe only a dev_dbg() because many developers complain that there are already too many debug messages in the boot logs. > Thanks, > Marcin >