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Date: Wed, 21 Dec 2016 16:11:20 -0800
From: Stephen Boyd <sboyd@codeaurora.org>
To: gabriel.fernandez@st.com
Cc: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
        Russell King <linux@armlinux.org.uk>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
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        Michael Turquette <mturquette@baylibre.com>,
        Nicolas Pitre <nico@linaro.org>, Arnd Bergmann <arnd@arndb.de>,
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        radoslaw.pietrzyk@gmail.com, devicetree@vger.kernel.org,
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        linux-clk@vger.kernel.org, kernel@stlinux.com, ludovic.barre@st.com,
        olivier.bideau@st.com, amelie.delaunay@st.com
Subject: Re: [PATCH v4 7/9] clk: stm32f4: SDIO & 48Mhz clock management for
 STM32F469 board
Message-ID: <20161222001120.GV8288@codeaurora.org>
References: <1481638820-29324-1-git-send-email-gabriel.fernandez@st.com>
 <1481638820-29324-8-git-send-email-gabriel.fernandez@st.com>
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On 12/13, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
> from pll-sai-p.
> 
> The SDIO clock could be also derived from 48Mhz or from sys clock.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---

Applied to clk-stm32f4 and merged into clk-next

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