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From: Andy Lutomirski <luto@amacapital.net>
Date: Fri, 23 Dec 2016 17:57:12 -0800
Message-ID: <CALCETrWpo2Sydy1q1i4SLLmT-m8oGUj_j79cW0NZyr2dSs1qJw@mail.gmail.com>
Subject: Re: [v2 1/7] x86/mpx: Do not use SIB index if index points to R/ESP
To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>, Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@suse.de>, Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        X86 ML <x86@kernel.org>, linux-msdos@vger.kernel.org,
        wine-devel@winehq.org, Dave Hansen <dave.hansen@linux.intel.com>,
        Adam Buchbinder <adam.buchbinder@gmail.com>,
        Colin Ian King <colin.king@canonical.com>,
        Lorenzo Stoakes <lstoakes@gmail.com>,
        Qiaowei Ren <qiaowei.ren@intel.com>,
        "Ravi V . Shankar" <ravi.v.shankar@intel.com>
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On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri
<ricardo.neri-calderon@linux.intel.com> wrote:
> Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software
> Developer's Manual volume 2A states that when memory addressing is used
> (i.e., mod part of ModR/M is not 3), a SIB byte is used and the index of
> the SIB byte points to the R/ESP (i.e.,index = 4), the index should not be
> used in the computation of the memory address.
>
> An example of such instruction could be
>
>     insn -0x80(%rsp)
>
> This is represented as:
>
>      [opcode] 4c 24 80
>
>       ModR/M: mod: 1, reg: 1: r/m: 4 (R/ESP)
>       SIB 24: sc: 0, index: 100 (R/ESP), base(R/ESP): 100
>       Displacement -0x80
>
> The correct address is (base) + displacement; no index is used.
>
> Care is taken to allow R12 to be used as index, which is a valid scenario.

Since I have no idea what this patch has to do with the rest of the
series, I'll ask a question:

Why isn't this code in the standard x86 instruction decoder?  Is the
decoder similarly buggy?