Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755597AbcLZJ1S (ORCPT ); Mon, 26 Dec 2016 04:27:18 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:37720 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750890AbcLZJ1M (ORCPT ); Mon, 26 Dec 2016 04:27:12 -0500 To: , xiakaixu 00238161 , , "linux-kernel@vger.kernel.org" , From: "Wangnan (F)" Subject: coresight: Problem caused by resetting enable_sink Message-ID: <6598d4c2-bbfb-1792-d216-a15ab0e841e0@huawei.com> Date: Mon, 26 Dec 2016 17:17:08 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.111.194.139] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1552 Lines: 55 Hi Mathieu, I meet problems caused by your commit d52c9750f150 ('coresight: reset "enable_sink" flag when need be'). Not only the one I posted in the previous patch. My use case is a simple 'perf record -e cs_etm// ls'. It works properly before this commit, and failed when allocating aux buffer after your commit. I can't fully understand your code, but the problem I meet seems caused by inappropriately reseting sink. My device is connected like this (use two etfs): Core0--+ Core1--+-- funnel0 --> etf0 Core2--| Core3--+ Core0--+ Core1--+-- funnel1 --> etf1 Core2--| Core3--+ Before running perf, two etfs are activated using sysfs enable_sink interface. During etm_setup_aux, coresight_get_enabled_sink() finds etf0 for core0, and automatically deactivates it. For core1, coresight_get_enabled_sink() returns etf1. However, etf1 is not on the link of core1, so following coresight_build_path() fails. I guess your commit is based on the assumption that all sinks are in the patch for each cores. Like this: Core0--+ Core1--+-- funnel0 --> etf0 ++ Core2--| | +--- etr Core3--+ | | + replicator + Core0--+ | | Core1--+-- funnel1 --> etf1 ++ +--- etb Core2--| Core3--+ But it is not true, at least for some hisilicon board. I have to revert your patch to make CoreSight on my board work. Please reconsider this patch, or please give some suggestion if you think I misunderstood your patch. Thank you.