Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751973AbcL1SMo (ORCPT ); Wed, 28 Dec 2016 13:12:44 -0500 Received: from mail-vk0-f45.google.com ([209.85.213.45]:34314 "EHLO mail-vk0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751840AbcL1SMn (ORCPT ); Wed, 28 Dec 2016 13:12:43 -0500 MIME-Version: 1.0 In-Reply-To: <20161228125354.GA30537@nazgul.tnic> References: <2f771739-a617-0870-2f68-2a8ebba0bc46@ce.jp.nec.com> <20161228111830.GA21788@nazgul.tnic> <20161228112120.GC21788@nazgul.tnic> <20161228125354.GA30537@nazgul.tnic> From: Andy Lutomirski Date: Wed, 28 Dec 2016 10:12:22 -0800 Message-ID: Subject: Re: [PATCH 3/2] x86/microcode/intel: Add a helper which gives the microcode revision To: Borislav Petkov Cc: Junichi Nomura , Boris Ostrovsky , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2171 Lines: 56 On Wed, Dec 28, 2016 at 4:53 AM, Borislav Petkov wrote: > On Wed, Dec 28, 2016 at 12:21:20PM +0100, Borislav Petkov wrote: >> From: Borislav Petkov >> >> Intel supplies the microcode revision value in MSR 0x8b >> (IA32_BIOS_SIGN_ID) after CPUID(1) has been executed. Execute it each >> time before reading that MSR. > > And then, we can go a step further and even do a separate helper which does the > required steps to read out the microcode revision so that we don't forget them > next time we change the code. > > Provided that works for xen, though, because I need to do the native > variants but early_init_intel() can call the paravirt *msr() versions > and I have no idea whether that's kosher on xen pv. > > Boris, any objections? > > --- > From: Borislav Petkov > Date: Wed, 28 Dec 2016 13:44:56 +0100 > Subject: [PATCH] x86/microcode/intel: Add a helper which gives the microcode > revision > > Since on Intel we're required to do CPUID(1) first, before reading > the microcode revision MSR, let's add a special helper which does the > required steps so that we don't forget to do them next time, when we > want to read the microcode revision. > > Signed-off-by: Borislav Petkov > --- > arch/x86/include/asm/microcode_intel.h | 15 ++++++++++++ > arch/x86/kernel/cpu/intel.c | 11 +++------ > arch/x86/kernel/cpu/microcode/intel.c | 43 ++++++++++------------------------ > 3 files changed, 31 insertions(+), 38 deletions(-) > > diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h > index 195becc6f780..e793fc9a9b20 100644 > --- a/arch/x86/include/asm/microcode_intel.h > +++ b/arch/x86/include/asm/microcode_intel.h > @@ -52,6 +52,21 @@ struct extended_sigtable { > > #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) > > +static inline u32 intel_get_microcode_revision(void) > +{ > + u32 rev, dummy; > + > + native_wrmsrl(MSR_IA32_UCODE_REV, 0); > + > + /* As documented in the SDM: Do a CPUID 1 here */ > + native_cpuid_eax(1); As in the other email, could this just be native_cpuid()? --Andy