Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752452AbcL2G55 (ORCPT ); Thu, 29 Dec 2016 01:57:57 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34344 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbcL2G5z (ORCPT ); Thu, 29 Dec 2016 01:57:55 -0500 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 62D4F6137F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=vivek.gautam@codeaurora.org MIME-Version: 1.0 In-Reply-To: <20161228230150.GB17126@codeaurora.org> References: <1482253431-23160-1-git-send-email-vivek.gautam@codeaurora.org> <1482253431-23160-3-git-send-email-vivek.gautam@codeaurora.org> <20161228230150.GB17126@codeaurora.org> From: Vivek Gautam Date: Thu, 29 Dec 2016 12:27:53 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/4] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips To: Stephen Boyd Cc: "robh+dt" , kishon , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Mark Rutland , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1505 Lines: 43 On Thu, Dec 29, 2016 at 4:31 AM, Stephen Boyd wrote: > On 12/20, Vivek Gautam wrote: >> PHY transceiver driver for QUSB2 phy controller that provides >> HighSpeed functionality for DWC3 controller present on >> Qualcomm chipsets. >> >> Signed-off-by: Vivek Gautam > > One comment below, but otherwise > > Reviewed-by: Stephen Boyd > >> +static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) >> +{ >> + struct device *dev = &qphy->phy->dev; >> + u8 *val; >> + >> + /* >> + * Read efuse register having TUNE2 parameter's high nibble. >> + * If efuse register shows value as 0x0, or if we fail to find >> + * a valid efuse register settings, then use default value >> + * as 0xB for high nibble that we have already set while >> + * configuring phy. >> + */ >> + val = nvmem_cell_read(qphy->cell, NULL); >> + if (IS_ERR(val) || !val[0]) { >> + dev_dbg(dev, "failed to read a valid hs-tx trim value, %ld\n", >> + PTR_ERR(val)); > > If val is 0 PTR_ERR(0) will be junk? I guess that's ok for debug > print. May be -EINVAL is better for debug print. Even when val[0] is 0, val will still be a valid pointer, and so PTR_ERR(val) will essentially be the pointer casted to long. Thanks Vivek -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project