Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752766AbcL2Jcm (ORCPT ); Thu, 29 Dec 2016 04:32:42 -0500 Received: from mga05.intel.com ([192.55.52.43]:35915 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752723AbcL2Jcj (ORCPT ); Thu, 29 Dec 2016 04:32:39 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,426,1477983600"; d="scan'208";a="47724107" From: Liang Li To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, kirill.shutemov@linux.intel.com, dave.hansen@linux.intel.com, guangrong.xiao@linux.intel.com, pbonzini@redhat.com, rkrcmar@redhat.com, Liang Li Subject: [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Date: Thu, 29 Dec 2016 17:26:00 +0800 Message-Id: <1483003563-25847-2-git-send-email-liang.z.li@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483003563-25847-1-git-send-email-liang.z.li@intel.com> References: <1483003563-25847-1-git-send-email-liang.z.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=y Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2167 Lines: 46 Define the related bits for the 5 level page table, which supports 57 bits width virtual address space. This patch maybe included in Kirill's patch set which enables 5 level page table for x86, because 5 level EPT doesn't depend on 5 level page table, we put it here for independence. Signed-off-by: Liang Li Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Kirill A. Shutemov Cc: Dave Hansen Cc: Xiao Guangrong Cc: Paolo Bonzini Cc: "Radim Krčmář" --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/uapi/asm/processor-flags.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index eafee31..2cf4018 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -288,6 +288,7 @@ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ +#define X86_FEATURE_LA57 (16*32 + 16) /* 5-level page tables */ #define X86_FEATURE_RDPID (16*32+ 22) /* RDPID instruction */ /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index 567de50..185f3d1 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -104,6 +104,8 @@ #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) +#define X86_CR4_LA57_BIT 12 /* enable 5-level page tables */ +#define X86_CR4_LA57 _BITUL(X86_CR4_LA57_BIT) #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ -- 1.9.1